Z8F3201VN020SC00TR Zilog, Z8F3201VN020SC00TR Datasheet - Page 143
Z8F3201VN020SC00TR
Manufacturer Part Number
Z8F3201VN020SC00TR
Description
IC ENCORE MCU FLASH 32K 44PLCC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F3201VN020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F3201VN020SC00T
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Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
®
Z8 Encore!
125
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address
data is transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address
and continues operating.
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral
control register must be an even address.
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
request transfer. The corresponding interrupts do not need to be enabled within the Inter-
rupt Controller to initiate a DMA transfer. However, if the Request Trigger Source can
enable or disable the interrupt request sent to the Interrupt Controller, the interrupt request
must be enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data. DMA1
Control register: UART0 Transmit Data register empty.
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
2
2
110 = DMA0 Control register: I
C Receiver Interrupt. DMA1 Control register: I
C Trans-
mitter Interrupt register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register contains the low byte of the on-chip peripheral address
for data transfer. The full 12-bit Register File address is given by {FH, DMAx_IO[7:0]}.
PS017610-0404
Direct Memory Access Controller
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