Z8F3201VN020SC00TR Zilog, Z8F3201VN020SC00TR Datasheet - Page 17

• Manufacturer Part Number: Z8F3201VN020SC00TR
• Description: IC ENCORE MCU FLASH 32K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3201VN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F3201VN020SC00T

PS017610-0404
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some com-
bination of smaller registers, buses, or individual bits.
•
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
•
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
•
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical may not be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
•
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least sig-
nificant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text.
•
•
•
Example: the 12-bit register address {
hexadecimal value (
(RP) and Working Register R1.
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Example: assume PC[15:0] contains the value
contents of the memory location at address
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Example 1: Stop mode.
Example 2: The receiver forces the SCL line to Low.
The Master can generate a Stop condition to abort the transfer.
0H
) and two 4-bit register values taken from the Register Pointer
0H
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
is the most significant nibble (4-bit value) of the
0H
, RP[7:4], R1[3:0]} is composed of a 4-bit
1234h
1234h
.
. (PC[15:0]) then refers to the
Manual Objectives
Z8 Encore!
®
xvii