Z8F3201VN020SC00TR Zilog, Z8F3201VN020SC00TR Datasheet - Page 201
Z8F3201VN020SC00TR
Manufacturer Part Number
Z8F3201VN020SC00TR
Description
IC ENCORE MCU FLASH 32K 44PLCC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F3201VN020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F3201VN020SC00T
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Assembly Language Syntax
eZ8 CPU Instruction Notation
PS017610-0404
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually has
the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol-
lowing instruction examples illustrate the format of some basic assembly instructions and
the resulting object code produced by the assembler. This binary format must be followed
by users that prefer manual program coding or intend to implement their own assembler.
Example 1: If the contents of Registers 43H and 08H are added and the result is stored in
43H, the assembly syntax and resulting object code is:
Table 113. Assembly Language Syntax Example 1
Example 2: In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0 - 255 or, using Escaped Mode
Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is:
Table 114. Assembly Language Syntax Example 2
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 115
Assembly Language Code ADD
Object Code
Assembly Language Code ADD
Object Code
; value
; Register at address
04
04
01H
, is the source. The value
43H,
08
43H,
E8
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
234H
08H
43
R8
43
.
(ADD dst, src)
(OPC src, dst)
(ADD dst, src)
(OPC src, dst)
01H
is written into the
eZ8 CPU Instruction Set
Z8 Encore!
®
183
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