LH7A400N0G000B5 Sharp Microelectronics, LH7A400N0G000B5 Datasheet
LH7A400N0G000B5
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LH7A400N0G000B5 Summary of contents
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Data Sheet FEATURES • ARM922T™ Core: – 32-bit ARM9TDMI™ RISC Core (200 MHz) – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) • 80KB On-Chip Memory • Programmable Interrupt Controller • External Bus Interface ...
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LH7A400 ARM922T STATIC (ASYNCHRONOUS) MEMORY CONTROLLER (SMC) PCMCIA/CF EXTERNAL CONTROLLER BUS INTERFACE SYNCHRONOUS DYNAMIC RAM CONTROLLER (SDMC) LCD AHB BUS COLOR LCD CONTROLLER ADVANCED LCD INTERFACE HIGH-PERFORMANCE 2 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET ...
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System-on-Chip PBGA CABGA SIGNAL PIN PIN G7 C10 F11 M1 F14 H13 R14 J9 VDD I/O Ring Power M14 K15 J11 L7 J12 N6 F13 N8 B14 N12 E10 N13 B8 P11 H7 ...
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LH7A400 PBGA CABGA SIGNAL PIN PIN R11 P12 VDDA Analog Power for PLL N12 M10 P12 R13 VSSA Analog Ground for PLL T11 N11 D3 E4 nPOR Power On Reset User Reset; should be pulled HIGH for normal or H6 ...
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System-on-Chip PBGA CABGA SIGNAL PIN PIN L12 L11 D0 M15 L13 D1 N13 L14 D2 L16 K11 D3 L15 L16 D4 L14 K14 D5 H11 J15 D6 K12 J12 D7 J15 J10 D8 J13 H16 D9 J10 H14 D10 ...
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LH7A400 PBGA CABGA SIGNAL PIN PIN M13 L15 A2/SA0 K16 K12 A3/SA1 K15 K13 A4/SA2 K14 K16 A5/SA3 J8 J13 A6/SA4 J16 J11 A7/SA5 J14 J16 A8/SA6 • Asynchronous Address Bus • Synchronous Address Bus J9 H15 A9/SA7 H16 H10 ...
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System-on-Chip PBGA CABGA SIGNAL PIN PIN F9 C11 nRAS Synchronous Memory Row Address Strobe Signal HIGH A9 C9 DQM0 Synchronous Memory Data Mask DQM1 Synchronous Memory Data Mask DQM2 Synchronous Memory Data Mask ...
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LH7A400 PBGA CABGA SIGNAL PIN PIN • GPIO Port PC6/LCDHRLP • LCD Latch Pulse • GPIO Port PC7/LCDSPL • LCD Start Pulse Left M11 M9 PD0/LCDVD8 L11 K10 PD1/LCDVD9 K8 P10 PD2/LCDVD10 N11 T11 ...
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System-on-Chip PBGA CABGA SIGNAL PIN PIN • GPIO Port PG2/nPCIOR • I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in single or dual card mode • GPIO Port PG3/nPCIOW • I/O Write ...
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LH7A400 PBGA CABGA SIGNAL PIN PIN PH6/ • GPIO Port AC97RESET • Audio Codec (AC97) Reset • GPIO Port H PH7/nPC • Status Read Enable for PC Card (PCMCIA or STATRE CompactFlash) in single or ...
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System-on-Chip PBGA CABGA SIGNAL PIN PIN UART2 Receive Data Input. This pin is an output J7 G3 UARTRX2 for JTAG boundary scan only SSPCLK Synchronous Serial Port Clock J1 J6 SSPRX Synchronous Serial Port Receive J2 J7 ...
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LH7A400 LCD PBGA CABGA MONO 4-BIT DATA PIN PIN SIGNAL SINGLE PANEL K1 K2 LCDVD17 J5 K1 LCDVD16 R10 T13 LCDVD15 P10 R12 LCDVD14 T9 R11 LCDVD13 R9 T12 LCDVD12 N11 T11 LCDVD11 K8 P10 LCDVD10 L11 K10 LCDVD9 M11 ...
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System-on-Chip Table 4. 256-Ball PBGA Package Numerical Pin List BGA PIN SIGNAL A1 TDI A2 MMCDATA/MMSPIDOUT A3 MMCCLK/MMSPICLK A4 ACIN A5 VSS A6 PF0/INT0 A7 VDDC A8 A27/SCRST A9 DQM0 A10 SCLK A11 VSS A12 nSCS3 A13 A24 A14 ...
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LH7A400 Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL C14 nSCS0 C15 VSS C16 A21 D1 BATOK D2 nBATCHG D3 nPOR D4 WAKEUP D5 ACOUT D6 PF5/INT5/SCDETECT D7 nPWME1 D8 nOE D9 DQM2 D10 nWE3 D11 ...
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System-on-Chip Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL F11 A19 F12 D17 F13 VDD F14 A16/SB0 F15 D16 F16 A15/SA13 G1 COL2 G2 COL3 G3 VSS G4 COL4 G5 COL5 G6 VSSC G7 VDD ...
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LH7A400 Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL J8 A6/SA4 J9 A9/SA7 J10 D10 J11 VDD J12 VDD J13 D9 J14 A8/SA6 J15 D8 J16 A7/SA5 K1 PA1/LCDVD17 K2 PA2 K3 PA3 K4 VSS K5 ...
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System-on-Chip Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL M4 PB4/UARTDCD3 M5 VDD M6 PG3/nPCIOW M7 PG5/nPCCE1 M8 PG6/nPCCE2 M9 PE2/LCDVD6 M10 PE3/LCDVD7 M11 PD0/LCDVD8 M12 nCS3/nMMSPICS M13 A2/SA0 M14 VDD M15 D1 M16 A0/nWE1 ...
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LH7A400 Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL P15 XTAL32OUT P16 XTAL32IN R1 PC2/LCDVDDEN R2 PC7/LCDSPL R3 PG0/nPCOE R4 PH1/CFA8/PCRESET2 R5 PH6/nAC97RESET R6 LCDFP R7 LCDVD1 R8 LCDLP R9 PD4/LCDVD12 R10 PD7/LCDVD15 R11 VDDA R12 ...
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System-on-Chip Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL A1 ACOUT A2 ACBITCLK A3 PF7/INT7/PCRDY2 A4 PF6/INT6/PCRDY1 A5 PF0/INT0 A6 nPWME1 A7 A27/SCRST A8 DQM3 A9 DQM1 A10 CS7/SCKE0 A11 SCKE3 A12 D31 A13 nSWE A14 ...
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LH7A400 Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL C12 D28 C13 nSCS0 C14 A22 C15 A21 C16 A20 D1 nURESET D2 nEXTPWR D3 TDO D4 MMCDATA/MMSPIDOUT D5 VSS D6 PF5/INT5/SCDETECT D7 VDDC D8 A25/SCIO D9 nWE3 ...
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System-on-Chip Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL F7 VSS F8 nWE0 F9 VDD F10 VDDC F11 VDD F12 D19 F13 A17/SB1 F14 VDD F15 D16 F16 A15/SA13 G1 COL1 G2 COL0 G3 UARTRX2 G4 ...
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LH7A400 Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL J2 SSPFRM/nSSPFRM J3 SSPCLK J4 VDDC J5 PGMCLK J6 SSPRX J7 SSPTX J8 VDDC J9 VDD J10 D8 J11 A7/SA5 J12 D7 J13 A6/SA4 J14 VSS J15 D6 ...
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System-on-Chip Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL L13 D1 L14 D2 L15 A2/SA0 L16 D4 M1 PB1/UARTTX3 M2 PB2/UARTRX3 M3 PB3/UARTCTS3 M4 PB7/SMBCLK M5 PC3/LCDREV M6 PG0/nPCOE M7 PH2/nPCSLOTE1 M8 LCDVD0 M9 PD0/LCDVD8 M10 ...
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LH7A400 Table 5. 256-Ball CABGA Package Numerical Pin List CABGA PIN SIGNAL P7 PH6/AC97RESET P8 LCDVD1 P9 LCDENAB/LCDM P10 PD2/LCDVD10 P11 VDD P12 VDDA P13 nTEST1 P14 nCS0 P15 nTEST0 P16 nCS1 R1 PC2/LCDVDDEN R2 PC6/LCDHRLP R3 PG3/nPCIOW R4 PG6/nPCCE2 ...
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System-on-Chip ROM FLASH SRAM SDRAM COMPACT FLASH PC PCMCIA CARD SYSTEM DESCRIPTIONS ARM922T Processor ...
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LH7A400 14.7456 MHz MAIN OSC. 32.768 kHz RTC OSC. Figure 3. Clock and State Controller Block Diagram Power Modes The LH7A400 has three operational states: Run, Halt, and Standby. In Run mode, all clocks are hard- ware-enabled and the processor ...
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System-on-Chip AMBA APB BUS The AMBA APB bus is a lower-speed 32-bit-wide peripheral data bus. The speed of this bus is selectable divide-by-2, divide-by-4 or divide-by-8 of the speed of the AHB bus. EXTERNAL BUS INTERFACE ...
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LH7A400 F000.0000 ASYNCHRONOUS MEMORY (nCS0) SYNCHRONOUS MEMORY (nSCS2) E000.0000 SYNCHRONOUS MEMORY (nSCS1) D000.0000 SYNCHRONOUS MEMORY (nSCS0) C000.0000 B001.4000 RESERVED B000.0000 EMBEDDED SRAM RESERVED 8000.3800 8000.2000 AHB INTERNAL REGISTERS APB INTERNAL REGISTERS 8000.0000 ASYNCHRONOUS MEMORY (CS7) 7000.0000 ASYNCHRONOUS MEMORY (CS6) 6000.0000 ...
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System-on-Chip EXTERNAL TO INTERNAL TO THE LH7A400 THE LH7A400 SDRAM SRAM ADDRESS SDRAM ROM CONTROL Figure 5. External Bus Interface Block Diagram Data Sheet ARM922T ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC) EXTERNAL DATA PCMCIA/CF BUS SUPPORT INTERFACE (EBI) and SYNCHRONOUS ...
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LH7A400 The Asynchronous Memory Controller has six main functions: • Memory bank select • Access sequencing • Wait states generation • Byte lane write control • External bus interface • CompactFlash or PCMCIA interfacing. Synchronous Memory Controller The Synchronous memory ...
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System-on-Chip Direct Memory Access Controller (DMA) The DMA Controller interfaces streams from the fol- lowing three peripherals to the system memory: • USB (1 Tx and 1 Rx DMA Channel) • MMC (1 Tx and 1 Rx DMA Channel) ...
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LH7A400 Audio Codec Interface (ACI) The ACI provides: • A digital serial interface to an off-chip 8-bit CODEC • All the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the ...
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System-on-Chip Real Time Clock (RTC) The RTC can be used to provide a basic alarm func- tion or long time-base counter. This is achieved by gen- erating an interrupt signal after counting for a programmed number of cycles of ...
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LH7A400 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) Storage Temperature NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions ...
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System-on-Chip 245 240 235 230 225 220 215 210 205 200 195 25 35 Figure 6. Temperature/Voltage/Speed Chart Data Sheet ° TEMP ( C) Version 1.0 LH7A400 1.89 V (+5%) 1.80 V 1.71 V (-5%) 75 ...
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LH7A400 DC/AC SPECIFICATIONS (COMMERCIAL AND INDUSTRIAL) Unless otherwise noted, all data provided under commercial DC/AC specifications are based on -40°C to +85°C, VDDC = 1. 1.89 V, VDD = 3 3.6 V, VDDA = 1.71 V ...
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System-on-Chip CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 8 were derived under the conditions presented here. Maximum Specified Value The values ...
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LH7A400 AC Specifications All signals described in Table 10 relate to transi- tions after a reference clock signal. The illustration in Figure 7 represents all cases of these sets of mea- surement parameters. The reference clock signals in this design ...
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System-on-Chip SIGNAL TYPE LOAD ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ wait states × C) Output 50 pF Output 50 pF A[27:0] Output Output 50 pF D[31:0] Input nCS[3:0]/CS[7:6] Output 30 pF nWE[3:0] Output 30 pF nOE Output ...
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LH7A400 Table 10. AC Signal Characteristics (Cont’d) SIGNAL TYPE LOAD MMCCMD Output 100 pF MMCDATA Output 100 pF MMCDATA Input MMCCMD Input ACOUT/ACSYNC Output 30 pF ACIN Input ACBITCLK Input SSPFRM Input SSPTX Output 50 pF SSPRX Input ACOUT/ACSYNC Output ...
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System-on-Chip SMC Waveforms Figure 8 and Figure 9 show the waveform and timing for an External Asynchronous Memory Write. Note that the deassertion of nWE can precede the deassertion of 'C' HCLK A[27:0] D[31:0] nCS[3:0], CS[7:6] nWE[3:0] Figure 8. ...
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LH7A400 0 1 'C' HCLK A[27:0] D[31:0] tAS nCS[3:0, CS[7:6] nWE[3:0] 0 WAIT STATE, DATA LATCHED Figure 9. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100 tWC VALID ADDRESS tDW VALID DATA ...
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System-on-Chip 'C' HCLK A[27:0] D[31:0] nCS[3:0], CS[7:6] nOE Figure 10. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000) Data Sheet tRC VALID ADDRESS DATA tAA LATCHED HERE VALID DATA tAS tCO tOE ...
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LH7A400 ' HCLK A[27:0] tAA D[31:0] tAS tCO nCS[3:0, CS[7:6] tOE nOE Figure 11. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100 tRC VALID ADDRESS DATA LATCHED HERE VALID DATA ...
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System-on-Chip Synchronous Memory Controller Waveforms Figure 12 shows the waveform and timing for a Syn- chronous Burst Read (page already open). Figure 13 shows the waveform and timing for Synchronous mem- ory to Activate a Bank and Write. t ...
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LH7A400 PC Card (PCMCIA) Waveforms Figure 14 shows the waveforms and timing for a PCMCIA Read Transfer, Figure 15 shows the wave- forms and timing for a PCMCIA Write Transfer. HCLK A[25:0] nPCREG nPCCEx (See Note 2) PCDIR D[15:0] nPCOE ...
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System-on-Chip HCLK A[25:0] nPCREG nPCCEx (See Note 2) PCDIR D[15:0] nPCWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 TRANSFER TYPE 0 0 Common Memory 0 1 Attribute Memory 1 0 ...
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LH7A400 MMC Interface Waveforms Figure 16 shows the waveforms and timing for an MMC command or data Write, and Figure 17 shows the waveforms and timing for an MMC command or data Read. MMCCLK MMCCMD MMCDAT MMCCLK MMCCMD MMCDAT ACBITCLK ...
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System-on-Chip Audio Codec Interface Waveforms Figure 19 and Figure 20 show the timing for the ACI. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A404 ACI ACBITCLK ACSYNC/ACOUT ACBITCLK ACSYNC BIT ACIN/ACOUT Data ...
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LH7A400 Clock and State Controller (CSC) Waveforms Figure 21 shows the behavior of the LH7A400 when coming out of Reset or Power On. Figure 22 shows exter- nal reset timing, and Table 11 gives the timing parame- ters. Figure 23 ...
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System-on-Chip POWER 2 sec. WAKEUP (asynchronous) CLKEN HCLK INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal ...
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LH7A400 INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. ...
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System-on-Chip Printed Circuit Board Layout Practices LH7A400 POWER SUPPLY DECOUPLING The LH7A400 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power ...
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LH7A400 PACKAGE SPECIFICATIONS 256-BALL PBGA TOP VIEW A1 BALL PAD CORNER A1 BALL PAD INDICATOR, 1.0 DIA. AVAILABLE MARKING AREA 2.90 ˚ 45 CHAMFER 4 PLACES BOTTOM VIEW (256 solder balls 1.00 REF. ...
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System-on-Chip 256-BALL CABGA TOP VIEW A1 BALL PAD CORNER BOTTOM VIEW (256 solder balls 1.0 NOTE: Dimensions in mm. Figure 28. 256-Ball CABGA Package Specification Data Sheet 0.10 (4X) 14. ...
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LH7A400 CONTENT REVISIONS This document contains the following changes to content, causing it to differ from previous versions. PAGE PARAGRAPH OR DATE NO. ILLUSTRATION 1 Features 3-11 Table 1 12 Table 3 12-18 Table 4 18-24 Table 5 39 Figure ...
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