LH7A400N0G000B5 Sharp Microelectronics, LH7A400N0G000B5 Datasheet - Page 38

• Manufacturer Part Number: LH7A400N0G000B5
• Description: IC ARM9 BLUESTREAK MCU 256PBGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0G000B5

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Maximum Clock Frequency: 250 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LH7A400
AC Specifications
tions after a reference clock signal. The illustration in
Figure 7 represents all cases of these sets of mea-
surement parameters.
• HCLK, internal System Bus clock (‘C’ in timing data)
• PCLK, Peripheral Bus clock
• SSPCLK, Synchronous Serial Port clock
• UARTCLK, UART Interface clock
• LCDDCLK, LCD Data clock from the
• ACBITCLK, AC97 clock
• SCLK, Synchronous Memory clock.
point of the clock to the 50% point of the signal.
38
LCD Controller
All signals described in Table 10 relate to transi-
The reference clock signals in this design are:
All signal transitions are measured from the 50%
REFERENCE
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
CLOCK
Figure 7. LH7A400 Signal Timing
tOVXXX
Version 1.0
represents the amount of time for the output to become
valid from a valid address bus, or rising edge of the
peripheral clock. Maximum requirements for tOVXXX
are shown in Table 10.
amount of time the output will be held valid from the valid
address bus, or rising edge of the peripheral clock. Min-
imum requirements for tOHXXX are listed in Table 10.
of time the input signal must be valid after a valid
address bus, or rising edge of the peripheral clock. Max-
imum requirements for tISXXX are shown in Table 10.
amount of time the output must be held valid from the
valid address bus, or rising edge of the peripheral
clock. Minimum requirements are shown in Table 10.
tISXXX tIHXXX
For outputs from the LH7A400, tOVXXX (e.g. tOVA)
The signal tOHXXX (e.g. tOHA) represents the
For Inputs, tISXXX (e.g. tISD) represents the amount
The signal tIHXXX (e.g. tIHD) represents the
tOHXXX
32-Bit System-on-Chip
Data Sheet
7A400-28