CY8C25122-24PXI Cypress Semiconductor Corp, CY8C25122-24PXI Datasheet - Page 38

• Manufacturer Part Number: CY8C25122-24PXI
• Description: IC MCU 4K FLASH 256B 8-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C25xxxr

Specifications of CY8C25122-24PXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.1.5
The Phase-Locked Loop (PLL) function generates the
system clock with crystal accuracy. It is designed to pro-
vide a 23.986 MHz oscillator when utilized with an exter-
nal 32.768 kHz crystal. Although the PLL provides
crystal accuracy it requires time to lock onto the refer-
ence frequency when first starting. After the External
Crystal Oscillator has been selected and enabled, the
following procedure should be followed to enable the
PLL and allow for proper frequency lock:
7.2
There are twelve system-clocking signals that are used
throughout the device. Referenced frequencies are
Table 39:
38
48M
24M
24V1
24V2
32K
CPU
SLP
Signal
Phase-Locked Loop (PLL) Operation
System Clocking Signals
System Clocking Signals and Definitions
The direct 48 MHz output from the Internal Main Oscillator.
The direct 24 MHz output from the Internal Main Oscillator.
The 24 MHz output from the Internal Main Oscillator that has been passed through a user-selectable 1
to 16 divider {F = 24 MHz / (1 to 16) = 24 MHz to 1.5 MHz}. The divider value is found in the Oscillator
Control 1 Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the
register bits.
The 24V1 signal that has been passed through an additional user-selectable 1 to 16 divider {F = 24
MHz / ((1 to 16) * (1 to 16)) = 24 MHz to 93.7 kHz}. The divider value is found in the Oscillator Control 1
Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the register
bits.
The multiplexed output of either the Internal Low Speed Oscillator or the External Crystal Oscillator.
The output from the Internal Main Oscillator that has been passed through a divider that has 8 user
selectable ratios ranging from 1:1 to 1:256, yielding frequencies ranging from 24 MHz to 93.7 kHz.
The 32K system-clocking signal that has been passed through a divider that has 4 user selectable
ratios ranging from 1:2
to clock the sleep timer period.
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
6
to 1:2
15
, yielding frequencies ranging from 512 Hz to 1 Hz. This signal is used
Definition
1.
2.
3.
4.
If the proper settings are selected in PSoC Designer, the
above steps are automatically done in boot.asm .
based on use of 32.768 kHz crystal. The names of these
signals and their definitions are as follows:
Select a CPU frequency of 3 MHz or less.
Enable the PLL.
Wait at least 10 ms.
Set CPU to a faster frequency, if desired. To do this,
write the bits CPU[20] in the USC_CPU register.
The CPU frequency will immediately change when
these bits are set.
September 5, 2002