Z8F0223SJ005EG Zilog, Z8F0223SJ005EG Datasheet - Page 164

• Manufacturer Part Number: Z8F0223SJ005EG
• Description: IC ENCORE MCU FLASH 2K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0223SJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-4082; Z8F0223SJ005EG

PS024314-0308
START
Note:
OCD Data Format
OCD Auto-Baud Detector/Generator
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
•
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit as
displayed in
When responding to a request for data, the OCD may commence transmitting immediately
after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the
host must not actively drive the DBG pin High for more than 0.5 bit times. It is recom-
mended that, if possible, the host drives the DBG pin using an open-drain output.
To run over a range of baud rates (data bits per second) with various system clock
frequencies, the OCD contains an auto-baud detector/generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character
data bits), framed between High bits. The auto-baud detector measures this period and sets
the OCD baud rate generator accordingly.
The auto-baud detector/generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation with asynchronous
D0
point, the PA0/DBG pin can be used to autobaud and cause the device to enter
DEBUG mode. For more details, see
page 156.
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
Voltage Brownout reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP mode initiates a system reset
D1
Figure
80H
. The character
25.
D2
Figure 25. OCD Data Format
D3
80H
has eight continuous bits Low (one Start bit plus 7
OCD Unlock Sequence (8-Pin Devices Only)
D4
D5
Z8 Encore! XP
D6
Product Specification
D7
®
On-Chip Debugger
F0823 Series
STOP
on
154