MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 361

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.4.1 Polled LVI Operation
21.4.2 Forced Reset Operation
21.4.3 False Reset Protection
MC68HC908AB32
Freescale Semiconductor
—
Rev. 1.1
Address:
Reset:
In applications that can operate at V
software can monitor V
register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls below the LVI
more consecutive CPU cycles. In configuration register 1, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
The V
supply noise. In order for the LVI module to reset the MCU, V
remain at or below the LVI
cycles. V
MCU out of reset.
Read: LVIOUT
Write:
DD
$FE0F
Bit 7
0
DD
pin level is digitally filtered to reduce false resets due to power
must be above LVI
Figure 21-2. LVI I/O Register Summary
Low-Voltage Inhibit (LVI)
= Unimplemented
6
0
0
TRIPF
DD
level and remains at or below that level for 9 or
5
0
0
by polling the LVIOUT bit. In configuration
TRIPF
DD
TRIPR
to remain above the LVI
level for 9 or more consecutive CPU
4
0
0
DD
for only one CPU cycle to bring the
levels below the LVI
3
0
0
2
0
0
Low-Voltage Inhibit (LVI)
TRIPF
1
0
0
Technical Data
TRIPF
DD
level,
must
level,
Bit 0
0
0
361
DD