MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 377

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

23.7 EEPROM and Memory Characteristics
MC68HC908AB32
Freescale Semiconductor
Notes:
Low-voltage inhibit reset/recover hysteresis – target
POR rearm voltage
POR reset voltage
POR rise time ramp rate
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. Stop I
6. Pullups are disabled. Port B leakage is specified in
7. Maximum is highest voltage that POR is guaranteed.
8. Maximum is highest voltage that POR is possible.
9. If minimum V
Notes:
RAM data retention voltage
EEPROM programming time per byte
EEPROM erasing time per byte
EEPROM erasing time per block
EEPROM erasing time per bulk
EEPROM programming voltage discharge period
Number of programming operations to the same EEPROM
EEPROM write/erase cycles at 10ms write time (85°C)
EEPROM data retention after 10,000 write/erase cycles
loads. Less than 100 pF on all outputs. C
affects run I
than 100 pF on all outputs. C
I
V
1. Programming a byte more times than the specified maximum may affect the data integrity of that byte. The byte must
DD
DD
DD
byte before erase
be erased before it can be programmed again.
. Measured with PLL and LVI enabled.
= 5.0 Vdc
is reached.
DD
DD
measured using external square wave clock source (f
is measured with OSC1 = V
DD
DD
. Measured with all modules enabled.
±
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
Characteristic
DD
—
(8)
10%, V
(7)
Rev. 1.1
measured using external square wave clock source (f
(1)
Characteristic
(9)
SS
= 0 Vdc, T
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
(1)
SS
A
.
= T
L
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
to T
Electrical Specifications
H
, unless otherwise noted
23.10 ADC
V
Symbol
PORRST
R
V
H
BUS
POR
POR
Characteristics.
LVI
= 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
Symbol
t
t
EBLOCK
t
t
t
EEPGM
V
EBYTE
EBULK
EEFPV
BUS
RDR
—
—
—
0.02
Min
100
0
0
= 8.4 MHz). All inputs 0.2 V from rail. No dc
10,000
Typ
Min
100
0.7
10
10
10
10
10
—
150
—
—
—
(2)
Electrical Specifications
Max
—
—
—
—
—
—
—
—
8
Max
200
800
—
—
Technical Data
Cycles
Years
Unit
ms
ms
ms
ms
µs
—
V
V/ms
Unit
mV
mV
mV
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