MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 147

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

C7I–C0I — Input Capture/Output Compare x Interrupt Enable Bits
Read: Anytime
Write: Anytime
TOI — Timer Overflow Interrupt Enable Bit
PUPT — Timer Pullup Resistor Enable Bit
RDPT — Timer Drive Reduction Bit
TCRE — Timer Counter Reset Enable Bit
PR2, PR1, and PR0 — Timer Prescaler Select Bits
Freescale Semiconductor
This enable bit controls pullup resistors on the timer port pins when the pins are configured as inputs.
This bit reduces the effective output driver size which can reduce power supply current and generated
noise depending upon pin loading.
This bit allows the timer counter to be reset by a successful output compare 7 event.
If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1,
TOF never gets set even though TCNT counts from $0000 through $FFFF.
These three bits specify the number of ÷2 stages that are to be inserted between the module clock and
the timer counter. See
The newly selected prescale factor will not take effect until the next synchronized edge where all
prescale counter stages equal 0.
0 = Interrupt inhibited
1 = Hardware interrupt requested when TOF flag set
0 = Disable pullup resistor function
1 = Enable pullup resistor function
0 = Normal output drive capability
1 = Enable output drive reduction function
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
Address: $008D
Reset:
Read:
Write:
PR2
Figure 12-13. Timer Interrupt Mask 2 Register (TMSK2)
0
0
0
0
1
1
1
1
Bit 7
TOI
0
Table
= Unimplemented
12-3.
PR1
6
0
0
0
0
1
1
0
0
1
1
M68HC12B Family Data Sheet, Rev. 9.1
Table 12-3. Prescaler Selection
PUPT
5
0
PR0
0
1
0
1
0
1
0
1
RDPT
4
0
TCRE
3
0
Prescale Factor
Reserved
Reserved
16
32
1
2
4
8
PR2
2
0
PR1
1
0
Bit 0
PR0
0
Block Diagram
147