MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 43

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Addr.
$004C
$004D
$0046
$0047
$0048
$0049
$004A
$004B
$004E
$004F
$0050
$0051
Notes:
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
PWM Scale Register 1 (PWSCAL1)
PWM Channel Counter Register 0
PWM Channel Counter Register 1
PWM Channel Counter Register 2
PWM Channel Counter Register 3
PWM Channel Period Register 0
PWM Channel Period Register 1
PWM Channel Period Register 2
PWM Channel Period Register 3
PWM Scale Counter Register 1
PWM Channel Duty Register 0
PWM Channel Duty Register 1
Register Name
See page 132.
See page 132.
See page 133.
See page 133.
See page 133.
See page 133.
See page 134.
See page 134.
See page 134.
See page 134.
See page 135.
See page 135.
(PWSCNT1)
(PWCNT0)
(PWCNT1)
(PWCNT2)
(PWCNT3)
(PWPER0)
(PWPER1)
(PWPER2)
(PWPER3)
(PWDTY0)
(PWDTY1)
Figure 2-1. Register Map (Sheet 4 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
1
1
1
1
1
1
= Unimplemented
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
6
0
0
0
0
0
0
1
1
1
1
1
1
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
5
0
0
0
0
0
0
1
1
1
1
1
1
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
R
4
0
0
0
0
0
0
1
1
1
1
1
1
= Reserved
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
3
0
0
0
0
0
0
1
1
1
1
1
1
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
2
0
0
0
0
0
0
1
1
1
1
1
1
U = Unaffected
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
1
0
0
0
0
0
0
1
1
1
1
1
1
Registers
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
1
1
1
1
1
1
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