MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 185
MC912DT128ACPV
Manufacturer Part Number
MC912DT128ACPV
Description
IC 8MHZ 16 BIT MICROCONTROLLER
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DT128ACPV
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
KMC912DT128ACPV
Q1195202
Q1195202
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC912DT128ACPVE
Manufacturer:
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Quantity:
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12.9 Computer Operating Properly (COP)
MC68HC912DT128A — Rev 4.0
MOTOROLA
PCLK
Figure 12-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
÷
÷
÷
÷
÷
÷
÷
÷
2
2
2
2
2
2
2
2
BITS: SPR2, SPR1, SPR0
REGISTER: SP0BR
0:1:0
1:1:0
0:0:1
0:1:1
1:0:0
1:0:1
1:1:1
0:0:0
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this the part will reset. If any value other than
$55 or $AA is written, the part is reset.
COUNTER (PR0-PR4)
5-BIT MODULUS
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSCLK
Go to: www.freescale.com
EXTALi
ECLK
BCLK
BIT RATE
SPI
Clock Functions
SYNCHRONIZER
CLKSRC
CLKSW
÷
LOGIC
BKGD
PIN
2
BKGD DIRECTION
BKGD OUT
BKGD IN
and ATD1
TO ATD0
Computer Operating Properly (COP)
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmit 1: Detect falling edge,
count 6 E clocks while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 E clocks,
Drive out 1 E cycle pulse high,
high impedance output
MSCAN
CLOCK
Clock Functions
Technical Data
185
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