MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 407
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MC912DT128ACPV
Manufacturer Part Number
MC912DT128ACPV
Description
IC 8MHZ 16 BIT MICROCONTROLLER
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DT128ACPV
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
KMC912DT128ACPV
Q1195202
Q1195202
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DT128ACPVE
Manufacturer:
MEANWELL
Quantity:
1 000
Company:
Part Number:
MC912DT128ACPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68HC912DT128A — Rev 4.0
MOTOROLA
The user should be careful that the state of the BDMACT bit is not
unintentionally changed with the WRITE_NEXT firmware command. If it
is unintentionally changed from 1 to 0, it will cause a system runaway
because it would disable the BDM firmware ROM while the CPU12 was
executing BDM firmware. The following two commands show how
BDMACT may unintentionally get changed from 1 to 0.
WRITE_X with data $FEFE
WRITE_NEXT with data $C400
The first command writes the data $FEFE to the X index register. The
second command writes the data $C4 to the $FF00 INSTRUCTION
register and also writes the data $00 to the $FF01 STATUS register.
ENTAG — Tagging Enable
SDV — Shifter Data Valid
TRACE — Asserted by the TRACE1 command
CLKSW — BDMCLK Clock Switch
BDMACT becomes set as active BDM mode is entered so that the
BDM firmware ROM is enabled and put into the map. BDMACT is
cleared by a carefully timed store instruction in the BDM firmware as
part of the exit sequence to return to user code and remove the BDM
memory from the map. This bit has 4 clock cycles write delay.
Set by the TAGGO command and cleared when BDM mode is
entered. The serial system is disabled and the tag function enabled
16 cycles after this bit is written.
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = BDM is not active. BDM ROM and registers are not in map.
1 = BDM is active and waiting for serial commands. BDM ROM and
0 = Tagging not enabled, or BDM active.
1 = Tagging active. BDM cannot process serial commands while
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
0 = BDM system operates with BCLK.
registers are in map
tagging is active.
Go to: www.freescale.com
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