MC68HC908GR8CP Freescale Semiconductor, MC68HC908GR8CP Datasheet - Page 259

• Manufacturer Part Number: MC68HC908GR8CP
• Description: IC MCU FLASH 8BIT 8MHZ 4K 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908GR8 — Rev 4.0
MOTOROLA
CAUTION:
CAUTION:
DMARE — DMA Receive Enable Bit
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
DMATE — DMA Transfer Enable Bit
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
Freescale Semiconductor, Inc.
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
For More Information On This Product,
1 = DMA not enabled to service SCI receiver DMA service requests
0 = DMA not enabled to service SCI receiver DMA service requests
1 = SCTE DMA service requests enabled; SCTE CPU interrupt
0 = SCTE DMA service requests disabled; SCTE CPU interrupt
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
Serial Communications Interface (SCI)
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
requests disabled
requests enabled
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Serial Communications Interface (SCI)
Technical Data
I/O Registers
259