MC68HC908GR16CFJ Freescale Semiconductor, MC68HC908GR16CFJ Datasheet - Page 130
MC68HC908GR16CFJ
Manufacturer Part Number
MC68HC908GR16CFJ
Description
IC MCU 16K FLASH 8MHZ SPI 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GR16CFJE.pdf
(276 pages)
Specifications of MC68HC908GR16CFJ
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer:
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Input/Output Ports (PORTS)
PTCPUE1 and PTCPUE0 — Port C Input Pullup Enable Bits
12.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and three of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
PTD7–PTD0 — Port D Data Bits
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
130
These writable bits are software programmable to enable pullup devices on an input port bit.
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The PTD6/T2CH0–PTD7/T2CH1 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD6/T2CH0–PTD7/T2CH1 pins are timer
channel I/O pins or general-purpose I/O pin. See
The PTD4/T1CH0–PTD5/T1CH1 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD4/T1CH0–PTD5/T1CH1 pins are timer
channel I/O pins or general-purpose I/O pins. See
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
Alternative
Function:
Address:
Reset:
Read:
Write:
T2CH1
$0003
PTD7
Bit 7
Figure 12-13. Port D Data Register (PTD)
T2CH0
PTD6
6
MC68HC908GR16 Data Sheet, Rev. 5.0
T1CH1
PTD5
5
T1CH0
Unaffected by reset
PTD4
4
Chapter 18 Timer Interface Module
Chapter 18 Timer Interface Module
SPSCK
PTD3
3
PTD2
MOSI
2
PTD1
MISO
1
Freescale Semiconductor
PTD0
Bit 0
SS
(TIM).
(TIM).
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