MC68HC908GT16CFB Freescale Semiconductor, MC68HC908GT16CFB Datasheet - Page 84

• Manufacturer Part Number: MC68HC908GT16CFB
• Description: IC MCU 16K FLASH 8MHZ SPI 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 36
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal Clock Generator (ICG) Module)
In its typical configuration, the external oscillator requires five external components:
7.3.3.2 External Clock Input Path
The external clock input path is the means by which the microcontroller uses an external clock source.
The input to the path is the PTE4/OSC1 pin and the output is the external clock (ECLK). The path, which
contains input buffering, is enabled when the external clock generator enable signal (ECGEN) is set.
When not enabled, the PTE4/OSC1 pin reverts to its port function.
7.3.4 Clock Monitor Circuit
The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external
clock (ECLK) and the internal clock (ICLK) to determine if either clock source has been corrupted. The
clock monitor circuit, shown in
7.3.4.1 Clock Monitor Reference Generator
The clock monitor uses a reference based on one clock source to monitor the other clock source. The
clock monitor reference generator generates the external reference clock (EREF) based on the external
clock (ECLK) and the internal reference clock (IREF) based on the internal clock (ICLK). To simplify the
circuit, the low-frequency base clock (IBASE) is used in place of ICLK because it always operates at or
near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be
at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided
down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) and
external crystal enable (EXTXTALEN) bits in the CONFIG2 register, according to the rules in
84
1. Crystal, X
2. Fixed capacitor, C
3. Tuning capacitor, C
4. Feedback resistor, RB
5. Series resistor, R
•
•
•
be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.)
Clock monitor reference generator
Internal clock activity detector
External clock activity detector
Each signal (IBASE and ECLK) is always divided by four. A longer divider
is used on either IBASE or ECLK based on the EXTSLOW bit.
1
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
S
1
(Included in
2
(can also be a fixed capacitor)
Figure
7-5, contains these blocks:
Figure 7-4
NOTE
to follow strict Pierce oscillator guidelines and may not
Freescale Semiconductor
Table
7-2.