C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 111

• Manufacturer Part Number: C8051F331
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

13.4. System Clock Selection
The CLKSL bits in register OSCICN select which oscillator is used as the system clock. CLKSL0 must be
set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator may still
clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The
system clock may be switched on-the-fly between the internal and external oscillator, so long as the
selected oscillator is enabled and has settled. The internal oscillator requires little start-up time and may be
selected as the system clock immediately following the OSCICN write that enables the internal oscillator.
External crystals and ceramic resonators typically require a start-up time before they are settled and ready
for use as the system clock. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware
when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software
should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and
C modes typically require no startup time. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
Bits7-2:
Bits1-0:
Bit7
R
-
UNUSED. Read = 000000b, Write = don't care.
SEL[1:0]: System Clock Source Select Bits.
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN
bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD
bits in register OSCLCN.
11: reserved.
Bit6
R
-
Bit5
Figure 13.7. CLKSEL: Clock Select Register
R
-
Bit4
R
-
C8051F330/1, C8051F330D
Rev. 1.2
Bit3
R
-
Bit2
R
-
SEL1
R/W
Bit1
SEL0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xA9
111