C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 205

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C8051F331

Manufacturer Part Number
C8051F331
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet

Specifications of C8051F331

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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0
20.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging, Flash
programming, and boundary scan functions may be performed. This is possible because C2 communica-
tion is typically performed when the device is in the halt state, where all on-chip peripherals and user soft-
ware are stalled. In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P2.0)
pins. In most applications, external resistors are required to isolate C2 interface traffic from the user appli-
cation. A typical isolation configuration is shown in Figure 20.6.
The configuration in Figure 20.6 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The /RST pin on the target device is used as an input only.
/Reset (a)
Output (c)
Input (b)
Figure 20.6. Typical C2 Pin Sharing
C2 Interface Master
C8051F330/1, C8051F330D
Rev. 1.2
C2CK
C2D
C8051Fxxx
207

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