C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 121
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C8051F331
Manufacturer Part Number
C8051F331
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet
1.C8051F330R.pdf
(208 pages)
Specifications of C8051F331
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F331
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F331-GM
Manufacturer:
SiliconL
Quantity:
1 630
Part Number:
C8051F331-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
C8051F331-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Bits7-0:
Bits7-0:
Bits7-0:
P1.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis-
ter P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
P1.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 14.9. P0MDOUT: Port0 Output Mode Register
P1.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
Figure 14.10. P0SKIP: Port0 Skip Register
Figure 14.11. P1: Port1 Register
P1.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
C8051F330/1, C8051F330D
Rev. 1.2
P1.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
P1.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
P1.1
R/W
R/W
R/W
Bit1
Bit1
Bit1
(bit addressable)
P1.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
Reset Value
11111111
0xA4
0xD4
0x90
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