C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 89

• Manufacturer Part Number: C8051F331
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

10.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source
Program execution begins at location 0x0000.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Px.x
Px.x
(Section “19.3. Watchdog Timer Mode” on page 197
Reset Sources
System
Clock
Comparator 0
Section “13. Oscillators” on page 103
+
-
Detector
Missing
C0RSEF
Clock
V
(one-
shot)
Microcontroller
EN
DD Monitor and power-on resets, the /RST pin is driven low until the device
Extended Interrupt
CIP-51
Core
Handler
WDT
PCA
Figure 10.1. Reset Sources
EN
VDD
System Reset
Supply
Monitor
+
-
C8051F330/1, C8051F330D
Rev. 1.2
Enable
(Software Reset)
SWRSF
for information on selecting and configuring
details the use of the Watchdog Timer).
'0'
Power On
Reset
Operation
FLASH
Errant
(wired-OR)
Reset
Funnel
/RST
89