MC68HC711E9CFU2 Freescale Semiconductor, MC68HC711E9CFU2 Datasheet - Page 42

no-image

MC68HC711E9CFU2

Manufacturer Part Number
MC68HC711E9CFU2
Description
IC MCU 12K OTP 2MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9CFU2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Operating Modes and On-Chip Memory
IRV(NE) — Internal Read Visibility (Not E) Bit
PSEL[3:0] — Priority Select Bits
2.3.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are protected against
writes except under special circumstances.
reset or that must be written within the first 64 cycles after reset.
42
SMOD = 0
SMOD = 1
Operating
Mode
IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on
or off. In special test mode, IRVNE is reset to 1. In all other modes, IRVNE is reset to 0. For the
MC68HC811E2, this bit is IRV and only controls the internal read visibility function.
In single-chip modes this bit determines whether the E clock drives out from the chip. For the
MC68HC811E2, this bit has no meaning or effect in single-chip and bootstrap modes.
Refer to
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Register
Address
Chapter 5 Resets and
$x03C
$x03D
$x03C
$x03D
$x024
$x035
$x039
$x024
$x035
$x039
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
System configuration options (OPTION)
Highest priority I-bit interrupt
and miscellaneous (HPRIO)
RAM and I/O map register (INIT)
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
System configuration options (OPTION)
Highest priority I-bit interrupt and
miscellaneous (HPRIO)
RAM and I/O map register (INIT)
0
0
Special test
Single chip
Expanded
Bootstrap
Table 2-2. Write Access Limited Registers
Mode
Register Name
Interrupts.
M68HC11E Family Data Sheet, Rev. 5.1
0
1
IRVNE Out
of Reset
Table 2-2
0
0
0
1
Special test
Bootstrap
E Clock Out
lists registers that can be written only once after
of Reset
Bits [1:0], once only
Clear bits, once only
Bits [5:4], bits [2:0], once only
See HPRIO description
Yes, once only
See HPRIO description
On
On
On
On
in First 64 Cycles
Must be Written
1
1
of Reset
IRV Out
Off
Off
Off
On
0
1
Affects Only
IRVNE
IRV
IRV
Bits [7:2]
Set bits only
Bits [7:6], bit 3
See HPRIO description
All, set or clear
All, set or clear
All, set or clear
See HPRIO description
All, set or clear
Freescale Semiconductor
E
E
Anytime
Write
IRVNE Can
Be Written
Once
Once
Once
Once

Related parts for MC68HC711E9CFU2