MC68HC711E9CFU2 Freescale Semiconductor, MC68HC711E9CFU2 Datasheet - Page 59

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MC68HC711E9CFU2

Manufacturer Part Number
MC68HC711E9CFU2
Description
IC MCU 12K OTP 2MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9CFU2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
3.2.3 Digital Control
All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the analog
input to be converted, ADCTL bits indicate conversion status and control whether single or continuous
conversions are performed. Finally, the ADCTL bits determine whether conversions are performed on
single or multiple channels.
3.2.4 Result Registers
Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can be accessed by the
processor in the CPU. The conversion complete flag (CCF) indicates when valid data is present in the
result registers. The result registers are written during a portion of the system clock cycle when reads do
not occur, so there is no conflict.
3.2.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock or an
internal RC oscillator for synchronization. When E-clock frequency is below 750 kHz, charge leakage in
the capacitor array can cause errors, and the internal oscillator should be used. When the RC clock is
used, additional errors can occur because the comparator is sensitive to the additional system clock
noise.
3.2.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can repeat continuously or stop after one iteration. The conversion complete flag (CCF) is set after the
fourth conversion in a sequence to show the availability of data in the result registers.
the timing of a typical sequence. Synchronization is referenced to the system E clock.
Freescale Semiconductor
E CLOCK
0
CHANNEL, UPDATE
CONVERT FIRST
SAMPLE ANALOG INPUT
ADR1
12 E CYCLES
32
Figure 3-3. A/D Conversion Sequence
CONVERT SECOND
CHANNEL, UPDATE
M68HC11E Family Data Sheet, Rev. 5.1
ADR2
CYCLES
MSB
4
SUCCESSIVE APPROXIMATION SEQUENCE
BIT 6
CYC
64
2
BIT 5
CYC
CHANNEL, UPDATE
CONVERT THIRD
2
BIT 4
CYC
ADR3
2
BIT 3
CYC
2
BIT 2
CYC
2
96
BIT 1
CYC
CONVERT FOURTH
CHANNEL, UPDATE
2
CYC
LSB
ADR4
2
CYC
END
2
Figure 3-3
128 — E CYCLES
Overview
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