MC68HC711E9VFN2 Freescale Semiconductor, MC68HC711E9VFN2 Datasheet - Page 111

• Manufacturer Part Number: MC68HC711E9VFN2
• Description: IC MCU 12K OTP 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9VFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.3.4 Clock Monitor Reset
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
Complete this 2-step reset sequence to service the COP timer:
Performing instructions between these two steps is possible as long
as both steps are completed in the correct sequence before the timer
times out.
The clock monitor circuit is based on an internal resistor capacitor (RC)
time delay. If no MCU clock edges are detected within this RC time
delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled or disabled by the CME control bit in
the OPTION register. The presence of a timeout is determined by the RC
delay, which allows the clock monitor to operate without any MCU
clocks.
Clock monitor is used as a backup for the COP system. Because the
COP needs a clock to function, it is disabled when the clock stops.
Therefore, the clock monitor system can detect clock failures not
detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E-clock frequency below 10 kHz
is detected as a clock monitor error. An E-clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E-clock is below 200 kHz is not recommended.
Reset:
Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST)
Read:
Write:
1. Write $55 to COPRST to arm the COP timer clearing mechanism.
2. Write $AA to COPRST to clear the COP timer.
$103A
Bit 7
Bit 7
0
Resets and Interrupts
Bit 6
6
0
Bit 5
5
0
Bit 4
4
0
Bit 3
3
0
Bit 2
2
0
Resets and Interrupts
Bit 1
1
0
Technical Data
Resets
Bit 0
Bit 0
0
111