C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 341
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C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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25. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 25.1 can
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084 Flash Address
0x0085
Bit15
Flash Control
JTAG Register Definition 25.1. IR: JTAG Instruction Register
Instruction
Flash Scale
PRELOAD
Flash Data
SAMPLE/
EXTEST
IDCODE
BYPASS
Selects the Boundary Data Register for control and observability of all
device pins
Selects the Boundary Data Register for observability and presetting the
scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds
to reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the Flash one-shot timer and
read-always enable
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Description
C8051F130/1/2/3
Bit0
Reset Value
0x0000
341
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