C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 342
C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
25.1. Boundary Scan
The DR in the Boundary Scan path is an 134-bit shift register. The Boundary DR provides control and
observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and
SAMPLE commands.
342
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
108, 110, 112, 114,
22, 24, 26, 28, 30,
23, 25, 27, 29, 31,
38, 40, 42, 44, 46,
39, 41, 43, 45, 47,
54, 56, 58, 60, 62,
55, 57, 59, 61, 63,
70, 72, 74, 76, 78,
71, 73, 75, 77, 79,
86, 88, 90, 92, 94,
87, 89, 91, 93, 95,
6, 8, 10, 12, 14,
7, 9, 11, 13, 15,
102, 104, 106,
96, 98, 100
97, 99, 101
16, 18, 20
17, 19, 21
32, 34, 36
33, 35, 37
48, 50, 52
49, 51, 53
64, 66, 68
65, 67, 69
80, 82, 84
81, 83, 85
116
Bit
0
1
2
3
4
5
Table 25.1. Boundary Data Register Bit Definitions
Action
Capture Reset Enable from MCU (64-pin TQFP devices)
Update
Capture Reset input from
Update
Capture Reset Enable from MCU (100-pin TQFP devices)
Update
Capture Reset input from
Update
Capture External Clock from XTAL1 pin
Update
Capture Weak pullup enable from MCU
Update
Capture P0.n output enable from MCU (e.g. Bit6=P0.0, Bit8=P0.1, etc.)
Update
Capture P0.n input from pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)
Update
Capture P1.n output enable from MCU
Update
Capture P1.n input from pin
Update
Capture P2.n output enable from MCU
Update
Capture P2.n input from pin
Update
Capture P3.n output enable from MCU
Update
Capture P3.n input from pin
Update
Capture P4.n output enable from MCU
Update
Capture P4.n input from pin
Update
Capture P5.n output enable from MCU
Update
Capture P5.n input from pin
Update
Capture P6.n output enable from MCU
Update
Target
Reset Enable to
Reset output to
Reset Enable to
Reset output to
Not used
Weak pullup enable to Port Pins
P0.n output enable to pin (e.g. Bit6=P0.0oe, Bit8=P0.1oe, etc.)
P0.n output to pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)
P1.n output enable to pin
P1.n output to pin
P2.n output enable to pin
P2.n output to pin
P3.n output enable to pin
P3.n output to pin
P4.n output enable to pin
P4.n output to pin
P5.n output enable to pin
P5.n output to pin
P6.n output enable to pin
RST
RST
RST
RST
RST
RST
Rev. 1.4
pin (64-pin TQFP devices)
pin (100-pin TQFP devices)
pin (64-pin TQFP devices)
pin (100-pin TQFP devices)
pin (64-pin TQFP devices)
pin (100-pin TQFP devices)
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