M30262F8GP#U5 Renesas Electronics America, M30262F8GP#U5 Datasheet - Page 124
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M30262F8GP#U5
Manufacturer Part Number
M30262F8GP#U5
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M30262F4GPU3.pdf
(41 pages)
3.M30262F4GPU3.pdf
(241 pages)
Specifications of M30262F8GP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30262F8GP#U5M30262F8GP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F8GP#U5M30262F8GP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F8GP#U5M30262F8GP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Serial I/O
116
Figure 1.15.8. Serial I/O-related registers (5)
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
UART transmit/receive control register 2
b7
b6
b5
Preliminary Specifications Rev. 0.9
b4
Specifications in this manual are tentative and subject to change.
b3
b2
b1
b0
Note 1: Nothing but 0 may be written.
Note 2: Underflow signal of timer A0 in UART2.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
CLKMD0
CLKMD1
RCSP
ABSCS
ACSE
U0RRM
U1RRM
symbol
SSS
Nothing is assigned.
In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.
symbol
U0IRS
U1IRS
ABC
BBS
IICM
(b3)
Bit
Bit
Symbol
* UART1 internal/external clock select bit (bit 3 at address 03A8
UCON
I
Arbitration lost detecting
flag control bit
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
Bus busy flag
Reserved bit
Bus collision detect
sampling
clock select bit
UART0 transmit
interrupt cause select bit
UART1 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
CLK/CLKS select
bit 1 (Note)
Separate CTS/RTS bit
2
U2SMR
Symbol
C mode select bit
Renesas Technology Corp.
name
name
Bit
Bit
Address
03B0
Address
16
0377
0 : STOP condition detected
1 : START condition detected
(During clock synchronous
0 : Normal mode
1 : I
0 : Update per bit
1 : Update per byte
Must always be 0.
Must always be 0
Must always be 0
Must always be 0
0 :
1 : Transmission completed
0 :
1 : Transmission completed
0 : Continuous receive
1 : Continuous receive
Valid when bit 5 = 1
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
1 : Transfer clock output
0 : CTS/RTS shared pin
1 : CTS/ RTS separated
(During clock synchronous
0 : Continuous receive
1 : Continuous receive
Transmit buffer empty (Tl = 1)
Transmit buffer empty (Tl = 1)
(CLK output is CLK1 only)
from multiple pins
function selected
16
(TXEPT = 1)
(TXEPT = 1)
mode disabled
mode enable
mode disabled
mode enabled
2
C mode
serial I/O mode)
serial I/O mode)
When reset
X0000000
Function
Function
When reset
X0000000
2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
0 : Rising edge of transfer
1 : Underflow signal of timer Aj
0 : Ordinary
1 : Falling edge of R
0 : No auto clear function
1 : Auto clear at occurrence of
Must always be 0
Must always be 0
Must always be 0
Must always be 0.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
Must always be 0
Invalid
Must always be 0
Must always be 0
0 : CTS/RTS shared pin
1 : CTS/ RTS separated
clock
bus collision
(TXEPT = 1)
(TXEPT = 1)
(During UART mode)
(During UART mode)
16
) = 0 .
Function
Function
X
M16C/26 Group
D
(Note 2)
i
(Note1)
R
R
W
W