M30262F8GP#U5 Renesas Electronics America, M30262F8GP#U5 Datasheet - Page 146
![IC M16C/TINY MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
M30262F8GP#U5
Manufacturer Part Number
M30262F8GP#U5
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M30262F4GPU3.pdf
(41 pages)
3.M30262F4GPU3.pdf
(241 pages)
Specifications of M30262F8GP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F8GP#U5M30262F8GP#D5
Manufacturer:
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Part Number:
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Quantity:
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Clock Asynchronous Serial I/O (UART) Mode
138
Figure 1.15.24. Typical transmit/receive timing in UART mode (used for SIM interface)
Note : Equal in waveform because TxD
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
RxD
Signal conductor level
(Note)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
RxD
TxD
Signal conductor level
(Note)
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
Note : Equal in waveform because TxD
2
2
2
2
Preliminary Specifications Rev. 0.9
Shown in ( ) are bit symbols.
Specifications in this manual are tentative and subject to change.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
1
0
1
0
1
0
1
0
1
0
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 0 .
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 1 .
1
0
1
0
ST
ST
Start
Start
ST
ST
bit
bit
D
D
D
D
0
0
0
0
2
Data is set in UART2 transmit buffer register
D
D
D
D
2
and RxD
1
1
1
1
Tc
Tc
and RxD
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
Renesas Technology Corp.
2
D
D
D
D
2
are connected.
4
4
4
4
are connected.
D
D
D
D
5
5
5
5
D
D
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
6
6
6
6
D
D
D
D
Parity
Parity
7
7
7
7
bit
bit
Tc = 16 (n + 1) / fi
Tc = 16 (n + 1) / fi
P
P
P
P
Cleared to 0 when interrupt request is accepted, or cleared by software
SP
Cleared to 0 when interrupt request is accepted, or cleared by software
SP
SP
SP
fi : frequency of BRG2 count source (f
n : value set to BRG2
fi : frequency of BRG2 count source (f
n : value set to BRG2
Stop
Stop
bit
bit
Read to receive buffer
ST
ST
ST
The level is detected by the
interrupt routine.
ST
An L level returns from TxD
the occurrence of a parity error.
An L level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
1SIO
1SIO
D
D
5
5
5
5
2
D
D
due to
2
D
D
, f
, f
6
6
due to
6
6
2SIO
2SIO
D
D
D
D
7
7
7
7
, f
, f
P
P
P
P
8SIO
8SIO
M16C/26 Group
Read to receive buffer
SP
SP
, f
, f
SP
SP
32SIO
32SIO
The level is
detected by the
interrupt routine.
)
)
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