MC9S08GT32CFDER Freescale Semiconductor, MC9S08GT32CFDER Datasheet - Page 104
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MC9S08GT32CFDER
Manufacturer Part Number
MC9S08GT32CFDER
Description
IC MCU 32K FLASH 2K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT32CFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Internal Clock Generator (ICG) Module
7.3.1.3
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
7.3.2
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f
into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f
mode is entered from FLL engaged internal, f
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f
If this mode is entered from off mode, f
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
104
•
•
•
•
ICGDCLK
After any reset.
Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
CLKS bits are written from X1 to 00.
CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
ICGDCLK
Self-Clocked Mode (SCM)
Stop/Off Mode Recovery
/ R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
MC9S08GB/GT Data Sheet, Rev. 2.3
ICGDCLK
ICGDCLK
ICGDCLK
will default to f
will be equal to the frequency of ICGDCLK before
will maintain the previous frequency.If this mode
Self_reset
which is nominally 8 MHz. If this
Freescale Semiconductor
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