MC9S08GT32CFDER Freescale Semiconductor, MC9S08GT32CFDER Datasheet - Page 160
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MC9S08GT32CFDER
Manufacturer Part Number
MC9S08GT32CFDER
Description
IC MCU 32K FLASH 2K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT32CFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Timer/PWM (TPM) Module
10.6.4
For channels that are configured for PWM operation, there are two possibilities:
The flag is cleared by the 2-step sequence described in
10.7
The TPM includes:
Each timer channel has:
Refer to the direct-page register summary in the
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some MCU systems have more than one TPM, so register names include placeholder characters to identify
which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x,
channel n and TPM1C2SC is the status and control register for timer 1, channel 2.
10.7.1
TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
160
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When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
An 8-bit status and control register (TPMxSC)
A 16-bit counter (TPMxCNTH:TPMxCNTL)
A 16-bit modulo register (TPMxMODH:TPMxMODL)
An 8-bit status and control register (TPMxCnSC)
A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
TPM Registers and Control Bits
PWM End-of-Duty-Cycle Events
Timer x Status and Control Register (TPMxSC)
Reset:
Read:
Write:
Figure 10-5. Timer x Status and Control Register (TPMxSC)
Bit 7
TOF
0
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
TOIE
6
0
CPWMS
Memory
5
0
Section 10.6.1, “Clearing Timer Interrupt
CLKSB
chapter of this data sheet for the absolute address
4
0
CLKSA
3
0
PS2
2
0
PS1
Freescale Semiconductor
1
0
Bit 0
PS0
0
Flags.”
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