TSH151ID STMicroelectronics, TSH151ID Datasheet - Page 4

• Manufacturer Part Number: TSH151ID
• Description: IC OPAMP SNGL MOS-INPUT 8-SOIC
• Manufacturer: STMicroelectronics

Specifications of TSH151ID

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 200 V/µs
• Gain Bandwidth Product: 150MHz
• Current - Input Bias: 2pA
• Voltage - Input Offset: 500µV
• Current - Supply: 25mA
• Current - Output / Channel: 100mA
• Voltage - Supply, Single/dual (±): ±3 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: 1
• Voltage Gain Db: 62.28 dB
• Common Mode Rejection Ratio (min): 60 dB
• Input Offset Voltage: 10 mV
• Supply Current: 30 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Maximum Dual Supply Voltage: +/- 6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: No
• Other names: 497-3067-5

TSH151
TEST WAVEFORM
PRINTED CIRCUIT LAYOUT
As for any high frequency device, a few rules must
be observed when designing the PCB to get the
best performances from this high speed op amp.
From the most to the least important points :
4/6
V
in
Each power supply lead has to be by-
passed to ground with a 10nF ceramic ca-
pacitor very close to the device and a 10 F
tantalum capacitor.
To provide low inductance and low resist-
ance common return, use a ground plane
or common point return for power and sig-
nal.
All leads must be wide and as short as pos-
sible especially for op amp inputs. This is in
50%
t
t
s
d
t
r
90%
10%
0.1% of edge amplitude
EVALUATION CIRCUIT
order to decrease parasitic capacitance
and inductance.
Use small resistor values to decrease time
constant with parasitic capacitance.
Choose component sizes as small as pos-
sible (SMD).
On output, decrease capacitor load so as
to avoid circuit stability being degraded
which may cause oscillation. You can also
add a serial resistor in order to minimise its
influence.
One can add in parallel with feedback re-
sistor a few pF ceramic capacitor C
ed to optimize the settling time.
Input
50
1k
-5V
+5V
1k
10nF
C
10 F
10nF
10 F
F
50
Output
F
adjust-