MAX6877ETG+ Maxim Integrated Products, MAX6877ETG+ Datasheet - Page 17

• Manufacturer Part Number: MAX6877ETG+
• Description: IC SEQUENCE/SUPERVISOR 24TQFN
• Manufacturer: Maxim Integrated Products
• Type: Sequencerr

Specifications of MAX6877ETG+

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Monitored Voltage: - 0.3 V to + 6 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1100 uA
• Maximum Power Dissipation: 1667 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During ramp up, if an OUT_ voltage is less than the ref-
erence ramp voltage by more than 125mV, the control
loop dynamically stops the control ramp voltage from
rising until the slow OUT_ voltage catches up. If an
OUT_ voltage is greater or less than the reference ramp
voltage by more than 250mV, a fault is signaled and a
power-down phase is initiated.
The slew rate for the reference ramp voltage is capaci-
tor adjustable. Connect a capacitor from SLEW to
ground to select the desired OUT_ slew rate. When all
OUT_ voltages have exceeded the V
of the IN_ voltage (external n-channel FET is saturated),
PG/RST asserts high after t
ful tracking.
The sequencing operation can be initiated after all
input conditions for power-up are met V
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period occurs as in
Figure 3 (programmable by connecting a capacitor
from DELAY to ground). The power-up phase for each
channel ends when its output voltage exceeds a fixed
percentage (V
When all channels have exceeded these thresholds,
PG/RST asserts high after t
cessful sequence.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
During power-up, the OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must be
completed within the adjustable fault timeout period; oth-
erwise, the part forces a shutdown on all GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing V
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than V
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
TRK
TH_PG
, the control loop dynamically stops the
______________________________________________________________________________________
) of the corresponding IN_ voltage.
Power-Up and Power-Down
TIMEOUT
TIMEOUT
EN/UV
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
indicating success-
, indicating a suc-
below V
TH_PG
EN/UV
Sequencing
percentage
EN_F
> 1.25V
. The
or less than the reference ramp voltage by more than
V
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_ and GATE _ is pulled low
with a strong I
Figures 5 and 6 show aborted tracking and sequencing
modes. When EN/UV goes low before t
expires, all the outputs go low and the device goes into
fast shutdown.
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below V
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
No external compensation is required for tracking or
slew-rate control.
The highest voltage on V
power to the device. The undervoltage threshold for
each IN_ supply is set with an external resistor-divider
from each IN_ to SET_ to ground.
The MAX6877 features three and the MAX6878/
MAX6879 feature two externally adjustable IN_ under-
voltage lockout (UVLO) thresholds (SET1, SET2, SET3) to
enable sequencing/tracking functionality. The undervolt-
age threshold for each IN_ supply is set with an exter-
nal resistor-divider from each IN_ to SET_ to ground
(see Figure 9). All SET_ inputs must be above the inter-
nal SET_ threshold (0.5V) to enable tracking/sequenc-
ing functionality. Use the following formula to set the
UVLO threshold:
where V
V
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
TRK_F
TH
is the 500mV SET threshold.
Undervoltage Lockout Threshold Inputs (SET_)
, a fault is signaled and the fast-shutdown mode
IN_
is the undervoltage lockout threshold and
GDS
V
IN_
current (see Figures 2 and 4).
= V
TH
CC
(R1 + R2) / R2
, IN1, IN2, or IN3 supplies
Margin Input
Stability Comment
Internal Pulldown
IN1/IN2/IN3
(M M A A R R G G I I N N )
TIMEOUT
Inputs
TH_PL
17