MAX16004ATP+ Maxim Integrated Products, MAX16004ATP+ Datasheet - Page 22

• Manufacturer Part Number: MAX16004ATP+
• Description: IC UP SUPERVISOR HEX 20-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Multi-Voltage Supervisorr

Specifications of MAX16004ATP+

• Number Of Voltages Monitored: 6
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 6 Selectable Threshold Combinations
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TQFN Exposed Pad
• Monitored Voltage: 1.8 V, 2.5 V, 3.3 V, Adjustable
• Undervoltage Threshold: 2.97 V, 2.25 V, 1.62 V, Adjustable
• Overvoltage Threshold: 1.71 V, 2.375 V, 3.135 V, Adjustable
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 50 uA
• Maximum Power Dissipation: 1355 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
The reset timeout period can be adjusted to accommo-
date a variety of µP applications from 50µs to 1.12s.
Adjust the reset timeout period (t
capacitor (C
reset timeout capacitor as follows:
Connect SRT to V
timeout of 140ms (min).
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to V
nected if not used. MR can be driven with TTL or
CMOS-logic levels, or with open-drain/collector out-
puts. Connect a normally open momentary switch from
Figure 15. Margin Output Disable (MARGIN) Affect on RESET Outside t
22
INTERNAL
MARGIN
SIGNAL
RESET
RESET
______________________________________________________________________________________
V
IN
SRT
V
C
TH
SRT
+ V
) between SRT and GND. Calculate the
t
TH_HYST
RP
CC
( )
F
for a factory-programmed reset
=
Reset Timeout Capacitor
Manual Reset Input (MR)
t
RP
(MAX16001/MAX16002/
MAX16004–MAX16007)
CC
V
TH SRT
( )
, so it can be left uncon-
s x I
_
SRT
RP
) by connecting a
V
TH
MR to GND to create a manual reset function. External
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environ-
ment, connecting a 0.1µF capacitor from MR to GND
provides additional noise immunity.
MARGIN allows system-level testing while power sup-
plies are adjusted from their nominal voltages. Drive
MARGIN low to force RESET, WDO, and OUT_ high,
regardless of the voltage at any monitored input. The
state of each output does not change while MARGIN =
GND. The watchdog timer continues to run when
MARGIN is low, and if a timeout occurs, WDO/RESET
will assert t
The MARGIN input is internally pulled up to V
MARGIN unconnected or connect to V
The MAX16000–MAX16007 operate from a 2.0V to 5.5V
supply. An undervoltage lockout ensures that the out-
puts are in the correct states when the UVLO is exceed-
ed. In noisy applications, bypass V
0.1µF capacitor as close to the device as possible. The
additional capacitor improves transient immunity. For
V
pass filter in front of V
RP
CC
transients with high slew rates, place an RC low-
V
TH
+ V
t
RP
TH_HYST
MD
Margin Output Disable ( MARGIN )
after MARGIN is deasserted.
CC
Power-Supply Bypassing
, where R can be up to 100Ω.
CC
CC
to ground with a
if unused.
CC
. Leave