X40415V8IZ-B Intersil, X40415V8IZ-B Datasheet
X40415V8IZ-B
Specifications of X40415V8IZ-B
Related parts for X40415V8IZ-B
X40415V8IZ-B Summary of contents
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... All other trademarks mentioned are the property of their respective owners. 4kbit EEPROM FN8116.0 and WDO RESET X40410/14 Power-on, RESET Reset X40411/15 V2FAIL Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved ™ pro- ...
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... Three com- mon low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications re- quiring higher precision ...
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PIN DESCRIPTION (Continued) Pin SOIC TSSOP Name 6 8 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output WDO WDO Output. WDO is an active LOW, open drain output which goes ...
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Figure 2. V Set/Reset Conditions TRIPX TRIPX WDO 0 SCL SDA A0h WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The micro- processor must toggle the ...
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Resetting the V Voltage TRIPx To reset a V voltage, apply the programming volt- TRIPx age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h ...
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Figure 5. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory ...
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BP: Block Protect Bit (Nonvolatile) The Block Protect Bit, BP, determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to half or ...
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Figure 6. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the ...
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Figure 7. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During ...
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Figure 9. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but ...
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Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data ...
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A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start shown in Figure 15. The device will go into standby mode after the stop and all ...
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Figure 15. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave – One bit of the slave command byte is a R/W bit. The R/W bit of ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ ...
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter V Supply CC ( Trip Point Voltage Range CC TRIP1 ( V2FAIL RPD2 TRIP2 Second Supply Monitor I V2MON Current V2 V ...
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EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT 4.6kΩ 2.06kΩ RESET SDA WDO 30pF 30pF A.C. TEST CONDITIONS Input pulse levels V Input rise and fall times 10ns Input and output timing levels V Output ...
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A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...
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Write Cycle Timing SCL th SDA 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence ...
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RESET/RESET Timings V TRIP1 PURST t R RESET V RVALID RESET LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Symbol ( RESET/RESET (Power-down only) RPD1 TRIP1 ( V2FAIL RPDX TRIP2 Power-on Reset delay: ...
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Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 20 X40410, X40411, X40414, X40415 Start Clockin ...
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Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t ...
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PACKAGING INFORMATION Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X40410, X40411, X40414, X40415 8-Lead Plastic, SOIC, Package Code S8 Pin 1 ...
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PACKAGING INFORMATION 0° – 8° .019 (.50) .029 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 X40410, X40411, X40414, X40415 8-Lead Plastic, TSSOP, Package Code V8 .025 (.65) BSC .169 (4.3) ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...