X40415V8IZ-B Intersil, X40415V8IZ-B Datasheet - Page 10

• Manufacturer Part Number: X40415V8IZ-B
• Description: IC VOLTAGE MON DUAL W/SUP 8TSSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40415V8IZ-B

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.3V, 2.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9. Byte Write Sequence
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
Figure 10. Page Write Operation
Figure 11. Writing 12 bytes to a 16-byte page starting at location 10.
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
Signals from
Signals from
the Master
the Slave
SDA Bus
Signals from
Signals from
7 Bytes
the Master
address
the Slave
SDA Bus
10
= 6
S
a
t
r
t
1 0 1 0
Address
Slave
X40410, X40411, X40414, X40415
0
S
a
t
r
t
address pointer
ends here
Addr = 7
0
0
Address
Slave
A
C
K
Address
Byte
0
A
C
K
Address
Byte
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master sup-
plies more than 16 bytes of data, then new data over-
writes the previous data, one byte at a time.
all inputs are disabled until completion of the internal
write cycle. See Figure 10 for the address, acknowl-
edge, and data transfer sequence.
address
A
C
K
10
Data
(1)
C
A
K
Data
(1 ≤ n ≤ 16)
C
A
K
5 Bytes
Data
address
(n)
A
C
K
n-1
S
o
p
t
A
C
K
S
o
p
t
March 28, 2005
FN8116.0