X40415V8IZ-B Intersil, X40415V8IZ-B Datasheet - Page 13

• Manufacturer Part Number: X40415V8IZ-B
• Description: IC VOLTAGE MON DUAL W/SUP 8TSSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40415V8IZ-B

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.3V, 2.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 15. Random Address Read Sequence
– One bit of the slave command byte is a R/W bit. The
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
– SDA pin is the input mode.
– RESET/RESET Signal is active for
Figure 16. Sequential Read Sequence
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
ble to write to the device.
Signals from
Signals from
the Master
the Slave
SDA Bus
Signals from
Signals from
the Master
the Slave
SDA Bus
13
Address
Slave
S
a
t
r
t
1
1 0 1
A
C
K
Address
Slave
t
X40410, X40411, X40414, X40415
0
PURST
0
Data
(1)
0
.
A
C
K
Address
C
A
K
Byte
Data
(2)
A
C
K
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
– A three step sequence is required before writing into
S
a
t
r
t
prior to the stop bit in order to start a nonvolatile
write cycle.
the Control Register to change Watchdog Timer or
Block Lock settings.
Address
A
C
K
Slave
(n is any integer greater than 1)
Data
(n-1)
1
C
A
K
Data
C
A
K
Data
(n)
S
o
p
t
March 28, 2005
S
o
p
t
FN8116.0