X40030S14IZ-B Intersil, X40030S14IZ-B Datasheet - Page 14

• Manufacturer Part Number: X40030S14IZ-B
• Description: IC VOLTAGE MONITOR TRPL 14-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40030S14IZ-B

• Number Of Voltages Monitored: 3
• Output: Push-Pull, Totem Pole
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.8V, 2.6V, 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read Operation
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is
followed by an acknowledge from the device and then by the
8-bit word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. See Figure 11 for the address, acknowledge, and
data transfer sequence.
Serial Device Addressing
Slave Address Byte
Following a start condition, the master must output a Slave
Address Byte. This byte consists of several parts:
• a device type identifier that is always ‘1011’.
• 1-bit (AS) that provides the device select bit. AS bit is set to
• next bit is ‘0’.
• last bit of the slave command byte is a R/W bit. The R/W
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to
• SDA pin is the input mode.
• RESET/RESET Signal is active for t
“0” as factory default.
bit of the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
write to the device.
FROM THE
FROM THE
SIGNALS
SDA BUS
SIGNALS
MASTER
SLAVE
14
S
A
R
T
T
1 0 1 1 0 0
PURST
ADDRESS
FIGURE 11. RANDOM ADDRESS READ SEQUENCE
SLAVE
X40030, X40031, X40034, X40035
.
0
A
C
K
1 1 1
ADDRESS
BYTE
1 1 1 1
1
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The WEL bit must be set to allow write operations.
• The proper clock count and bit sequence is required prior
• A three step sequence is required before writing into the
• The WP pin, when held HIGH, prevents all writes to the
A
C
K
CONTROL REGISTER
FAULT DETECTION
REGISTER
CONTROL REGISTER
FAULT DETECTION
REGISTER
FIGURE 12. X40030, X40031, X40034, X40035 ADDRESSING
to the stop bit in order to start a nonvolatile write cycle.
Control Register to change Watchdog Timer or Block Lock
settings.
array and all the Register.
S
T
A
R
T
ADDRESS
SLAVE
1
A
C
K
SLAVE BYTE
WORD ADDRESS
1
1
1
1
DATA
0
0
1
1
1
1
1
1
1
1
1
1
S
O
P
T
0
0
1
1
0
0
1
1
August 25, 2008
1
0
1
1
FN8114.2
R/W
R/W
1
1