X40235S16I-A Intersil, X40235S16I-A Datasheet
X40235S16I-A
Specifications of X40235S16I-A
Related parts for X40235S16I-A
X40235S16I-A Summary of contents
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... Tap DCP R COUNTER W REGISTER 8 - BIT NONVOLATILE MEMORY R H WIPER Optional COUNTER R W REGISTER 64 or 100 Tap DCP 8 - BIT NONVOLATILE MEMORY V3FAIL V2FAIL RESET Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved CC is stable ...
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X40231, X40233, X40235, X40237, X40239 PIN CONFIGURATION SINGLE XDCP X40231 16 Pin SOIC RESET V3MON 14 V2FAIL V3FAIL 4 13 V2MON ...
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X40231, X40233, X40235, X40237, X40239 X40231 PIN ASSIGNMENT SOIC Name Connect Connect V3MON Voltage Monitor Input. V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than ...
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X40231, X40233, X40235, X40237, X40239 X40233 PIN ASSIGNMENT SOIC Name Connect Connect V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than 3 ...
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X40231, X40233, X40235, X40237, X40239 X40235 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP. W2 ...
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X40231, X40233, X40235, X40237, X40239 X40237 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP2 Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP2. W2 ...
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X40231, X40233, X40235, X40237, X40239 X40239 PIN ASSIGNMENT SOIC Name R 1 Connection to end of resistor array for (the 256 Tap) DCP2 Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP2. W2 ...
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... Data Stable Data Change Valid Data Changes on the SDA Bus Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy, either by Intersil at final test or by the user during their devices production process. Some distributors offer V reprogramming as a value added service ...
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X40231, X40233, X40235, X40237, X40239 SCL SDA Figure 2. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and ...
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X40231, X40233, X40235, X40237, X40239 Depending upon the operation to be performed on each of these individual parts Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on ...
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X40231, X40233, X40235, X40237, X40239 Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK returned? YES NO High Voltage Cycle complete. Continue command sequence? YES Continue normal Read or ...
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X40231, X40233, X40235, X40237, X40239 TRANS 0 A nonvolatile write to a DCP will change the “wiper posi- tion” by simultaneously writing new data to the associ- ated WCR and NVM. Therefore, the new “wiper position” setting ...
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X40231, X40233, X40235, X40237, X40239 SLAVE ADDRESS BYTE T Figure 9. DCP Write Operation A write to DCPx (x=0,1,2) can be performed using the three byte command sequence shown ...
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X40231, X40233, X40235, X40237, X40239 S Signals from t Slave the Master a Address r t SDA Bus Signals from the Slave DCP Read Operation A read of DCPx (x = 0,1,2) can be performed using ...
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X40231, X40233, X40235, X40237, X40239 S Signals from t a the Master r t SDA Bus Signals from the Slave Figure 12. EEPROM Page Write Operation EEPROM Byte Write In order to perform an EEPROM Byte Write operation to the ...
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X40231, X40233, X40235, X40237, X40239 7 bytes Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11. Signals from the Master Figure 14. Current EEPROM Address Read Sequence Current EEPROM Address Read Internally the device contains ...
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X40231, X40233, X40235, X40237, X40239 Signals from S the Master SDA Bus Signals from the Slave Figure 15. Random EEPROM Address Read Sequence The master terminates the read operation ...
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X40231, X40233, X40235, X40237, X40239 CS3 CS7 CS6 CS4 CS5 PUP1 BL1 V2FS V3FS BL0 Bit(s) Description WEL Write Enable Latch bit RWEL Register Write Enable Latch bit V2FS V2MON Output Flag Status V3FS V3MON Output Flag ...
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X40231, X40233, X40235, X40237, X40239 When the Block Lock bits of the CR register are set to something other than BL1 = 0 and BL0 = 0, then the “wiper position” of the DCPs cannot be changed - i.e. DCP ...
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X40231, X40233, X40235, X40237, X40239 Prior to writing to the CR register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps —Write a 02H to the CR Register to ...
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X40231, X40233, X40235, X40237, X40239 MR: Manual Reset The RESET output can be forced HIGH externally using the Manual Reset (MR) input de-bounced, TTL compatible input, and so it may be operated by con- necting a push-button ...
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X40231, X40233, X40235, X40237, X40239 V2MON Monitoring The X4023x asserts the V2FAIL output HIGH if the voltage V2MON exceeds the corresponding V threshold (See Figure 21). The bit V2FS in the CR reg- ister is then set to a “0” ...
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X40231, X40233, X40235, X40237, X40239 Setting a Higher V Voltage (x = 1,2,3) TRIPx To set a V threshold to a new voltage which is TRIPx higher than the present threshold, the user must apply the desired V threshold voltage ...
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X40231, X40233, X40235, X40237, X40239 For example, the desired threshold for V 3.0 V, and a test voltage of 3.4 V was applied to the input pin V2MON (after applying power to V age is decreased, and found to trip ...
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X40231, X40233, X40235, X40237, X40239 ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on WP pin (With respect to VSS) Voltage on other pins (With respect to VSS) Voltage Voltage ...
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X40231, X40233, X40235, X40237, X40239 TIMING DIAGRAMS Figure 27. Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT Figure 28. WP Pin Timing START SCL SDA IN WP Figure 29. Write Cycle Timing SCL 8th bit ...
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X40231, X40233, X40235, X40237, X40239 Figure 30. Power-Up and Power-Down Timing Volts RESET 0 Volts MR 0 Volts Figure 31. Manual Reset Timing Diagram MR RESET V CC Figure 32. V2MON, V3MON Timing Diagram t ...
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X40231, X40233, X40235, X40237, X40239 Figure 33. V Programming Timing Diagram (x=1,2,3). TRIPX V , V2MON, V3MON CC t TSU VPS SCL SDA NOTE : V1/V Figure 34. DCP “Wiper Position” Timing Rwx (x=0,1,2) R WX(n) ...
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X40231, X40233, X40235, X40237, X40239 D.C. OPERATING CHARACTERISTICS Symbol Parameter V CC Current into V Pin (X4023x: Active) CC (1) I Read memory array CC 1 Write nonvolatile memory V Current into V Pin (X4023x:Standby) CC With 2-Wire bus activity ...
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X40231, X40233, X40235, X40237, X40239 A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29) Symbol f SCL Clock Frequency SCL (5) t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time ...
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X40231, X40233, X40235, X40237, X40239 POTENTIOMETER CHARACTERISTICS Symbol Parameter R End to End Resistance Tolerance TOL V R Terminal Voltage (x = 0,1,2) RHx Terminal Voltage (x = 0,1,2) RLx L (1) P Power Rating R R ...
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X40231, X40233, X40235, X40237, X40239 1,2,3) PROGRAMMING PARAMETERS (See Figure 33) TRIPX Parameter t V Program Enable Voltage Setup time VPS TRIPx t V Program Enable Voltage Hold time VPH TRIPx t V Setup time TSU TRIPx ...
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X40231, X40233, X40235, X40237, X40239 APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Tap Position Decimal ...
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X40231, X40233, X40235, X40237, X40239 APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. unsigned DCP1_TAP_Position(int tap_pos) { int block; int i; int offset; int wcr_val; offset = 0; block = tap_pos / 25; if (block ...
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X40231, X40233, X40235, X40237, X40239 16-Lead Plastic, SOIC (300-mil body), Package Code S16 PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) (4X) 7° 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0° ° 0.015 (0.40) 0.050 (1.27) ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...