X40235S16I-A Intersil, X40235S16I-A Datasheet - Page 5

• Manufacturer Part Number: X40235S16I-A
• Description: IC VOLTAGE MON TRPL EE 16-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40235S16I-A

• Number Of Voltages Monitored: 3
• Output: Open Drain, Open Drain
• Reset: Active High/Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.75V, 2.2V, 2.95V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

X40235 PIN ASSIGNMENT
SOIC
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
V3MON
V2MON
V3FAIL
V2FAIL
RESET
Name
SDA
R
SCL
VSS
V
R
MR
WP
NC
NC
NC
W2
CC
H2
Connection to end of resistor array for (the 256 Tap) DCP.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than
the V
not used.
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires
the use of an external “pull-up” resistor.
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET
pin (V
normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The
MR pin requires the use of an external “pull-down” resistor.
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and
the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile
or nonvolatile) operations can be performed in the device (including the wiper position of any of the
integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,
thus if left floating the write protection feature is disabled.
Serial Clock.
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA
pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
No Connect
No Connect
No Connect
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than
the V
not used.
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
LOW when V2MON is less than V
The V2FAIL pin requires the use of an external “pull-up” resistor.
V
This is an active HIGH, open drain output which becomes active whenever V
RESET becomes active on power-up and remains active for a time t
stabilizes (t
The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
Supply Voltage.
CC
RESET Output.
TRIP3
TRIP2
5
CC
RESET Output pin). RESET will remain HIGH for time t
threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
X40231, X40233, X40235, X40237, X40239
PURST
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
TRIP2
. There is no power-uppower-up reset delay circuitry on this pin.
Function
PURST
PURST
after MR has returned to it’s
after the power supply
CC
falls below V
TRIP2
TRIP3
, and goes
TRIP1
and goes
SS
SS
April 11, 2005
when
when
.
FN8115.0