XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet
XC56309VL100A
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XC56309VL100A Summary of contents
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DSP56309 U ’ M SER S ANUAL DSP56309UM Rev. 1, December 2005 ...
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... Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale ...
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DSP56309 Overview Signals/Connections Memory Configuration Programming the Peripherals Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Triple Timer Module Programming Reference Core Configuration Bootstrap Program A B ...
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DSP56309 Overview Signals/Connections 2 3 Memory Configuration 4 Core Configuration 5 Programming the Peripherals 6 Host Interface (HI08) 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communication Interface (SCI) 9 Triple Timer Module Bootstrap Program A B Programming Reference ...
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... Host Interface (HI08 2-9 2.7.1 Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.7.2 Host Port Configuration 2-10 2.8 Enhanced Synchronous Serial Interface 0 (ESSI0 2-14 2.9 Enhanced Synchronous Serial Interface 1 (ESSI1 2-16 2.10 Serial Communication Interface (SCI 2-18 Freescale Semiconductor DSP56309 User’s Manual, Rev ...
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... JTAG Boundary Scan Register (BSR 4-34 5 Programming the Peripherals 5.1 Peripheral Initialization Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Mapping the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 Reading Status Registers 5-2 5.4 Data Transfer Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 vi DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Enhanced Synchronous Serial Interface (ESSI) 7.1 ESSI Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 ESSI Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.1 Serial Transmit Data Signal (STD 7-2 7.2.2 Serial Receive Data Signal (SRD 7-3 7.2.3 Serial Clock (SCK 7-3 Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 Contents vii ...
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... SCI Serial Clock (SCLK 8-4 8.3 SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.1 Preamble, Break, and Data Transmission Priority 8-7 8.4.2 Bootstrap Loading Through the SCI (Boot Mode $ 8-7 viii DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Timer Prescaler Count Register (TPCR 9-23 9.4.4 Timer Control/Status Register (TCSR 9-24 9.4.5 Timer Load Register (TLR 9-28 9.4.6 Timer Compare Register (TCPR 9-28 9.4.7 Timer Count Register (TCR 9-29 A Bootstrap Program A.1 Bootstrap Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 Contents ix ...
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... Contents B Programming Reference B.1 Internal I/O Memory Map .B-2 B.2 Interrupt Sources and Priorities .B-6 B.3 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-10 x DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... You can obtain these documents—and the Freescale DSP development tools—through a local Freescale Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Freescale web site at the address listed on the back cover of this manual. ...
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... See the appropriate data sheet for the range of acceptable high CC voltage levels (typically a TTL logic high). 1-2 Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted DSP56309 User’s Manual, Rev that CC . See CC Voltage 2 Ground Ground Freescale Semiconductor ...
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... Removed overbars from HA10, HRW, AA0–AA3, and TMS. Modified signal definitions. Changed the note at the end of Table 2-3. Modified signal definitions. In Table 2-8, changed the State During Reset, Stop, or Wait descriptions for the BR and BB signals. Freescale Semiconductor RESET Example 1-1. Sample Code Listing RESET Change DSP56309 User’ ...
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... DSP56309 User’s Manual, Rev. 1 Revision 0 Revision 1 Page Number Page Number Pages 2-17 to Pages 2-10 to 2-21 2-12 Page 2-22 to Page 2-13 to 2-31 2-19 Page 4-17 Page 4-13 Page 8-20 Page 8-21 Page D-13 Page B-11 Page D-33 Page B-30 Freescale Semiconductor ...
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... Fully-static design specified to operate down (dc) — Optimized power-management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) 1.6 DSP56300 Core Functional Blocks The functional blocks of the DSP56300 core are: Data arithmetic logic unit (ALU) Address generation unit Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 DSP56300 Core Functional Blocks 1-5 ...
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... The multiplier executes 24-bit signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit 1-6 24-bit parallel, fractional multiplies between twos-complement × DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Program interrupt controller. Arbitrates among all interrupt requests (internal interrupts, as well as the five external requests appropriate interrupt vector address. PCU features include the following: Position-independent code support Addressing modes optimized for DSP applications (including immediate offsets) Instruction cache controller Freescale Semiconductor , , , IRQA IRQB IRQC IRQD DSP56309 User’ ...
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... Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this standard. The test logic includes a TAP with four dedicated signals, a 16-state controller, and three test data registers. A boundary scan 1-8 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Further features of external memory include the following: External memory expansion port Simultaneous glueless interface to static random access memory (SRAM) and dynamic random access memory (DRAM) Freescale Semiconductor Table 1-3. Internal Memory Program RAM Instruction Size Cache Size 20480 × ...
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... Y memory address bus for carrying Y memory addresses throughout the core. The block diagram in Figure 1-1 illustrates these buses among other components. All internal buses on the DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit bus. 1-10 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... See Section 1.6.6, Internal Memory, on page 1-9 for memory size details. 1.8 DMA The DMA block has the following features: Six DMA channels supporting internal and external accesses One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals Freescale Semiconductor ESSI SCI Program RAM ...
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... ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. ESSI capabilities include the following: Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs Normal mode operation using frame sync 1-12 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Connection to the external world through one bidirectional signal. When this signal is configured as an input, the timer functions as an external event counter or measures external pulse width/signal period. When the signal is used as an output, the timer functions as either a timer, a watchdog pulse width modulator. Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 Peripherals 1-13 ...
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... DSP56309 Overview 1-14 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 4. Port E signals are the SCI port signals multiplexed with the GPIO signals. 5. The number of Ground signals listed are for the 144-pin TQFP package. For the 196-ball MAP-BGA package, there are 66 GND connections. Freescale Semiconductor Number of Signals ...
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... SC0[0–2] PC[0–2] SCK0 PC3 SRD0 PC4 STD0 PC5 Port D GPIO PD[0–2] SC1[0–2] PD3 SCK1 PD4 SRD1 STD1 PD5 Port E GPIO PE0 RXD TXD PE1 PE2 SCLK Timer GPIO TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE Freescale Semiconductor ...
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... Quiet Ground Q An isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections, except GND decoupling capacitors. Freescale Semiconductor Table 2-2. Power Inputs Description . The user must provide adequate external decoupling capacitors. CCP . The user must provide adequate external decoupling capacitors. ...
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... XTAL unconnected. DSP56309 User’s Manual, Rev The user must provide adequate external P1 . The user must provide adequate external . The user must provide adequate external ) are listed for the 144-pin TQFP S and GND are connected together inside P P1 Freescale Semiconductor ...
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... Type Name Stop, or Wait A[0–17] Output Tri-stated Freescale Semiconductor Table 2-5. Phase Lock Loop Signals Reset PLL Capacitor Connects an off-chip capacitor to the PLL filter. See the DSP56309 Technical Data sheet to determine the correct PLL capacitor value. Connect one capacitor terminal to PCAP and the other terminal to V ...
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... TAS bit in the Operating Mode Register (OMR). TA functionality cannot be used during DRAM-type accesses; otherwise improper operation may result. DSP56309 User’s Manual, Rev. 1 Signal Description Signal Description TA input is ignored. The TA input TA is deasserted at the start of a bus TA can operate Freescale Semiconductor ...
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... BCLK Output Tri-stated BCLK Output Tri-stated Freescale Semiconductor External Memory Expansion Port (Port A) Signal Description Bus Request Asserted when the DSP requests bus mastership and deasserted when the DSP no longer needs the bus. BR can be asserted or deasserted independently of whether the DSP56309 is a bus master or a bus slave. ...
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... OMR when the RESET signal is deasserted. Internally synchronized to CLKOUT. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the Wait state. MODB/IRQB can tolerate 5 V. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus. The HI08 supports a variety of standard buses and can directly connect to a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware. Freescale Semiconductor Signal Description Mode Select C/External Interrupt Request C ...
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... HI function is selected, these signals are lines 0–7 of the Address/Data bus. Port B 0–7 When the HI08 is configured as GPIO through the HPCR, these signals are individually programmed through the HI08 Data Direction Register (HDDR). This input tolerant. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... HA2 Input Ignored input HA9 Input PB10 Input or Output Freescale Semiconductor Signal Description 1,2 Host Address Input 0 When the HI08 is programmed to interface with a non-multiplexed host bus and the HI function is selected, this signal is line 0 of the Host Address bus. Host Address Strobe ...
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... When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 10 of the Host Address bus. Port B 13 When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed through the HDDR. This input tolerant. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Signal Description 1,2 Host Request When the HI08 is programmed to interface with a single host request host bus and the HI function is selected, this signal is the Host Request (HREQ) output ...
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... Port C 2 The default configuration following reset is GPIO. For PC2, signal direction is controlled through PRRC. This signal is configured as SC02 or PC2 through PCRC. This input tolerant. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Enhanced Synchronous Serial Interface 0 (ESSI0) Signal Description 1, 2 Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes, or the transmitter only in Asynchronous modes ...
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... Port D 2 The default configuration following reset is GPIO. For PD2, signal direction is controlled through PRRD. This signal is configured as SC12 or PD2 through PCRD. This input tolerant. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Description 1, 2 Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes, or the transmitter only in Asynchronous modes ...
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... Provides the input or output clock used by the transmitter and/or the receiver. Port E 2 The default configuration following reset is GPIO. For PE2, signal direction is controlled through the SCI PRRE. This signal is configured as SCLK or PE2 through PCRE. This input tolerant. DSP56309 User’s Manual, Rev. 1 Signal Description Freescale Semiconductor ...
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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Table 2-15. Triple Timer Signals Signal Description 1, 2 Timer 0 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO0 is input ...
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... Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input tolerant. DSP56309 User’s Manual, Rev. 1 Signal Description DE causes DE DE has an internal Freescale Semiconductor is ...
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... External Memory Interface (Port A), for details on using the external memory interface to access external program memory. Bootstrap program ROM (192 × 24-bit) Note: Program memory space at locations $FF00C0–$FFFFFF is reserved and should not be accessed. Freescale Semiconductor DSP56309 User’s Manual, Rev 3-1 ...
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... K program words switch to instruction cache and are not accessible via addressing; the address range switches to external program memory. 3.1.4 Program Bootstrap ROM The program memory space occupying locations $FF0000–$FF00BF includes the internal bootstrap ROM. This ROM contains the 192-word DSP56309 bootstrap program. 3-2 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... X I/O space and it can be accessed by move, movep instructions and by bit-oriented instructions (bchg, bclr, bset, btst, brclr, brset, bsclr, bsset, jclr, jset, jsclr, and jsset). The contents of the internal X I/O memory space are listed in Appendix A, Bootstrap Program. Freescale Semiconductor DSP56309 User’s Manual, Rev Data Memory Space ...
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... Address mode or $FF80–$FFFF in the 16-bit Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). 3-4 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... SC mode with regard to the reallocation of X and Y data memory to program memory in MS mode, but the maximum addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide. Freescale Semiconductor Dynamic Memory Configuration Switching CAUTION CAUTION DSP56309 User’ ...
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... Program Memory) $0000–$5FFF N/A $0000–$5BFF $5C00–$5FFF (internal location not accessible; addressed assigned to external Program Memory) DSP56309 User’s Manual, Rev data RAM Cache Cache Location N/A Freescale Semiconductor ...
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... Bootstrap ROM $FF0000 External $005000 Internal Program RAM 20 K $000000 Bit Settings Program RAM $0000–$4FFF Freescale Semiconductor DEFAULT X Data $FFFFFF $FFFFFF Internal I/O $FFFF80 $FFFF80 External $FFF000 $FFF000 Internal Reserved $FF0000 $FF0000 External $001C00 $001C00 Internal X data RAM ...
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... X data RAM 7 K $000000 $000000 Memory Configuration X Data RAM Y Data RAM $0000–$1BFF $0000–$1BFF DSP56309 User’s Manual, Rev Data External I/O External Internal Reserved External Internal Y data RAM 7 K Addressable Cache Memory Size internal not accessible Freescale Semiconductor ...
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... External $006000 Internal Program RAM 24 K $000000 Bit Settings Program RAM $0000–$5FFF Figure 3-3. Switched Program RAM ( Freescale Semiconductor X Data $FFFFFF $FFFFFF Internal I/O $FFFF80 $FFFF80 External $FFF000 $FFF000 Internal Reserved $FF0000 $FF0000 External $001400 $001400 Internal X data RAM ...
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... X data RAM 3 K $000000 $000000 Memory Configuration X Data RAM Y Data RAM $0000–$13FF $0000–$13FF DSP56309 User’s Manual, Rev Data External I/O External Internal Reserved External Internal Y data RAM 3 K Addressable Cache Memory Size internal not accessible Freescale Semiconductor ...
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... Internal Program RAM 20 K $0000 Bit Settings Program RAM $0000–$4FFF Figure 3-5. 16-bit Space with Default RAM ( Freescale Semiconductor X Data $FFFF $FFFF Internal I/O $FF80 $FF80 External $1C00 $1C00 Internal X data RAM 7 K $0000 $0000 Memory Configuration X Data RAM ...
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... Internal X data RAM 7 K $0000 $0000 Memory Configuration X Data RAM Y Data RAM $000–$1BFF $000–$1BFF DSP56309 User’s Manual, Rev Data External I/O External Internal Y data RAM 7 K Addressable Cache Memory Size internal not accessible Freescale Semiconductor ...
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... Internal Program RAM 24 K $0000 Bit Settings Program RAM $000–$7FF Figure 3-7. 16-bit Space with Switched Program RAM ( Freescale Semiconductor X Data $FFFF $FFFF Internal I/O $FF80 $FF80 External $1400 $1400 Internal X data RAM 5 K $0000 $0000 Memory Configuration ...
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... Internal X data RAM 5 K $0000 $0000 Memory Configuration X Data RAM Y Data RAM $0000–$13FF $0000–$13FF ( DSP56309 User’s Manual, Rev Data External I/O External Internal Y data RAM 5 K Addressable Cache Memory Size internal not accessible Freescale Semiconductor ...
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... Table 4-1 shows the DSP56309 bootstrap operation modes, the corresponding settings of the external operational mode signal lines (the OMR[MA–MD] bits), and the reset vector address to which the DSP56309 jumps once it leaves the Reset state. Freescale Semiconductor DSP56309 User’s Manual, Rev ...
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... The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 (HF0). This starts execution of the loaded program from the specified starting address. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
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... Freescale Semiconductor Reset MODA Vector 1 $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode The bootstrap program sets the host interface to interface with the Freescale HC11 microcontroller through the HI08. The HOST HC11 bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be loaded ...
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... The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 (HF0). This starts execution of the loaded program from the specified starting address. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
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... Freescale Semiconductor Reset MODA Vector 1 $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode The bootstrap program sets the host interface to interface with the Freescale HC11 microcontroller through the HI08. The HOST HC11 bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be loaded ...
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... The Operating Mode Register (OMR) configures several system operating modes and characteristics. 4-6 MODA MODA DSP56309 User’s Manual, Rev. 1 – signal lines and loads MODD – ) and the resulting MA, MODD Freescale Semiconductor ...
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... Freescale DSPs. Bit definitions in the following paragraphs identify the bits within the SR and not within the subregister. Extended Mode Register (EMR CP[1– Reset Reserved bit. Read as zero; write to zero for future compatibility Freescale Semiconductor Mode Register (MR S[1–0] I[1– Figure 4-1. Status Register (SR) DSP56309 User’ ...
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... In this mode, 16-bit data is right-aligned in the 24-bit memory locations, registers, and 24-bit register portions. Shifting, limiting, rounding, arithmetic instructions, and moves are performed accordingly. For details on Sixteen-Bit Arithmetic mode, consult the DSP56300 Family Manual . DSP56309 User’s Manual, Rev. 1 OMR SR (CP[1–0]) (CDP[1-0 Freescale Semiconductor ...
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... Freescale Semiconductor Description DO FOREVER Flag Set when a DO FOREVER loop executes. The FV flag, like the LF flag, is restored from the stack when a DO FOREVER loop terminates. Stacking and restoring the FV flag when initiating and exiting a DO FOREVER loop, respectively, allow program loops to be nested. When returning from the long interrupt with an RTI instruction, the system stack is pulled and the value of the FV bit is restored ...
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... Rounding Bit SEquation (A46 XOR A45) OR (B46 XOR B45 (previous (A47 XOR A46) OR (B47 XOR B46 (previous (A45 XOR A44) OR (B45 XOR B44 (previous) — S undefined Exceptions Exceptions Masked Permitted IPL None IPL IPL 0 IPL 2, 3 IPL 0, 1 IPL 3 IPL Freescale Semiconductor ...
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... Freescale Semiconductor Description Extension Cleared if all the bits of the integer portion of the 56-bit result are all ones or all zeros; otherwise, this bit is set. The Scaling mode defines the integer portion. If the E bit is cleared, then the low-order fraction portion contains all the significant bits ...
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... EOV flag is a sticky bit (that is, cleared only by hardware reset explicit MOVEC operation to the OMR). The transition of the EOV flag from zero to one causes a Priority Level 3 (Non-maskable) stack error exception. DSP56309 User’s Manual, Rev. 1 Chip Operating Mode (COM EBD Description Freescale Semiconductor 0 * ...
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... ABE 12 BRT 11 TAS Freescale Semiconductor 0 Stack Extension Underflow Flag Set when a stack underflow occurs in Extended Stack mode. Extended stack underflow is recognized when a pull operation is requested and the SEN bit enables Extended mode. The EUN flag is a sticky bit (that is, cleared only by hardware reset explicit MOVEC operation to the OMR). ...
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... Indicate the operating mode of the DSP56300 core. On hardware reset, these bits are loaded from the external mode select pins, MODD, MODC, MODB, and MODA, respectively. After the DSP56300 core leaves the Reset state, MD–MA can be changed under program control. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
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... There are two interrupt priority registers in the DSP56309. The IPRC (Figure 4-3) is dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56309 peripheral interrupt sources D5L1 D5L0 D4L1 D4L0 IDL2 IDL1 IDL0 ICL2 Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF) Freescale Semiconductor D3L1 D3L0 D2L1 D2L0 D1L1 ICL1 ...
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... S0L1 S0L0 Interrupts Masked No — Yes 0 Yes 0, 1 Yes DSP56309 User’s Manual, Rev reserved 1 0 HPL1 HPL0 HI08 IPL ESSI0 IPL ESSI1 IPL SCI IPL TRIPLE TIMER IPL reserved Interrupt Priority Level – the value of the IRQA IRQD Freescale Semiconductor ...
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... VBA:$38 0–2 VBA:$3A 0–2 VBA:$3C 0–2 VBA:$3E 0–2 VBA:$40 0–2 VBA:$42 0–2 Freescale Semiconductor Table 4-5. Interrupt Sources Interrupt Source Hardware RESET Stack error Illegal instruction Debug request interrupt Trap Nonmaskable interrupt (NMI) Reserved Reserved IRQA ...
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... SCI receive data with exception status SCI transmit data SCI idle line SCI timer Reserved Reserved Reserved Host receive data full Host transmit data empty Host command (default) Reserved : Reserved Interrupt Source Level 3 (nonmaskable) DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... ESSI1 transmit last slot interrupt ESSI1 TX data interrupt SCI receive data with exception interrupt SCI receive data SCI transmit data SCI idle line SCI timer TIMER0 overflow interrupt Freescale Semiconductor Interrupt Source Levels (maskable) DSP56309 User’s Manual, Rev. 1 Configuring Interrupts 4-19 ...
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... Controls the internal crystal oscillator XTAL output. The XTLD bit is cleared during DSP56309 hardware reset, so the XTAL output signal is active, permitting normal operation of the crystal oscillator. DSP56309 User’s Manual, Rev XTLR DF2 DF1 DF0 MF3 MF2 MF1 MF0 Freescale Semiconductor ...
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... BA2W1 BA2W0 BA1W4 BA1W3 Reserved bit. Read as zero; write to zero for future compatibility Figure 4-6. Bus Control Register (BCR) Freescale Semiconductor Description Crystal Range Controls the internal crystal oscillator transconductance. The XTLR bit is cleared (0) during hardware reset. Division Factor Define the DF of the low-power divider. These bits specify the power ...
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... When four through seven wait states are selected, one additional wait state is inserted at the end of the access. This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Figure 4-7. Note: To prevent improper device operation, you must guarantee that all the DCR bits except BSTR are not changed during a DRAM access. Freescale Semiconductor Description Bus Area 1 Wait State Control Defines the number of wait states (one through 31) inserted into each external SRAM access to Area 1 (DRAM accesses are not affected by these bits) ...
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... BRF[7–0] = $00 and BRP = 0 generates a refresh request every clock cycle, but a refresh access takes at least five clock cycles). DSP56309 User’s Manual, Rev BRF0 BSTR BREN BME BRW1 BRW0 BCW1 BCW0 . Freescale Semiconductor ...
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... BCW 0 Bus Column In-Page Wait State Defines the number of wait states to insert for each DRAM in-page access. The encoding of BCW[1–0] is: Freescale Semiconductor Description 00 = 9-bit column width, 512 words 01 = 10-bit column width words 10 = 11-bit column width words 11 = 12-bit column width words ...
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... BYEN BPEN BAAP BXEN Description DSP56309 User’s Manual, Rev BAC1 BAC0 Address to Compare 1 0 BAT1 BAT0 External Access Type AA pin polarity Program space Enable X data space Enable Y data space Enable Reserved Packing Enable Number of Address bit to compare Freescale Semiconductor ...
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... AA/RAS signal is active low or active high. When BAAP is cleared, the AA/RAS signal is active low (useful for enabling memory modules or for DRAM Row Address Strobe). If BAAP is set, the appropriate AA/RAS signal is active high (useful as an additional address bit). Freescale Semiconductor Description BPAC is used only for DMA accesses and not core accesses. 2. ...
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... When DIE is cleared, the DMA interrupt is disabled. 4-28 Description 00 = Reserved 01 = SRAM access 10 = DRAM access 11 = Reserved DTM0 DPR1 DPR0 DCON DAM3 DAM2 DAM1 DAM0 Description DSP56309 User’s Manual, Rev DRS4 DRS3 DRS2 DDS1 DDS0 DSS1 Freescale Semiconductor 12 DRS1 0 DSS0 ...
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... Note: When DTM = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is still processing the first request (see the description of the DRS bits). Freescale Semiconductor Description DE Trigger Cleared ] After request Yes Block Transfer— ...
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... SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0]. Priority of core accesses to external memory is as follows: 4-30 Description DPR 00 Priority level 0 (lowest Priority level 3 (highest) DSP56309 User’s Manual, Rev. 1 Channel Priority Priority level 1 Priority level 2 Freescale Semiconductor ...
Page 89
... DMA access even if the DMA does not need the bus in this cycle. However refresh cycle from the DRAM controller is requested, the refresh cycle interrupts the DMA transfer. When DCON is cleared, the priority algorithm operates as for the DPR bits. Freescale Semiconductor Description CP[1–0] 00 ...
Page 90
... Transfer done from channel 0 Transfer done from channel 1 Transfer done from channel 2 Transfer done from channel 3 Transfer done from channel 4 Transfer done from channel 5 SCI receive data (RDRF = 1) SCI transmit data (TDRE = 1) Timer0 (TCF0 = 1) Timer1 (TCF1 = 1) Timer2 (TCF2 = 1) Reserved Freescale Semiconductor ...
Page 91
... Figure 4-10 shows the contents of the IDR. Revision numbers are assigned as follows revision revision A, and so on Reserved $00 Figure 4-10. Identification Register Configuration (Revision E) Freescale Semiconductor Description In Cache mode, a DMA to Program memory space has some limitations (as described in Chapter 3, Memory Configuration . DDS1 DDS0 0 0 ...
Page 92
... BSR, consult the DSP56300 Family Manual. For the latest description of the BSR contents by available package type in boundary scan description language (BSDL), call your local Freescale Semiconductor Sales Office or authorized distributor or visit the Freescale Semiconductor web site listed on the back cover of this manual. ...
Page 93
... Referred to as the internal I/O space, the control registers are accessed by move (MOVE, MOVEP) instructions and bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). The Freescale Semiconductor DSP56309 User’s Manual, Rev ...
Page 94
... Data Transfer Methods Peripheral I/O on the DSP56309 can be accomplished in three ways: Polling Interrupts DMA 5-2 X-Data Memory Peripherals Control Registers Internal I/O Memory Space External Internal Reserved External Internal X-Data RAM 2 K (default) DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 95
... In this case, the program executes that service routine and continues until a return-from-interrupt (RTI) instruction executes. The execution flow then resumes from the position the program counter was in before the interrupt was triggered. Freescale Semiconductor Example 5-1. Software Polling ; loop if HSR[1]:HTDE=0 ; move data to x1 DSP56309 User’ ...
Page 96
... Depending on the peripheral, one to four peripheral request sources are available. This is the most efficient method of data transfer available. Core intervention is not required after the DMA channel is initialized. 5-4 Example 5-2. Interrupts DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 97
... I/O. An interrupt is generated when data is ready to be transferred to or from the peripheral device. DMA requires even less core intervention, and the setup code is minimal, but the DMA channels must be available. Note: Do not use interrupt requests and DMA requests simultaneously. Freescale Semiconductor Register TX0 TX1 TX2 ...
Page 98
... HA1 HA8 HA2 HA9 HCS/HCS HA10 Single DS Double DS HRW HRD/HRD HDS/HDS HWR/HWR Single HR Double HR HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ Figure 5-2. Port B Signals DSP56309 User’s Manual, Rev. 1 Port B GPIO PB[0–7] PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Freescale Semiconductor ...
Page 99
... Serial Interface Port 1 5.5.4 Port E Signals and Registers Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal. Three registers control the GPIO functionality of Port E: Port E control register (PCRE), Port E Freescale Semiconductor SC0[0–2] SCK0 SRD0 ...
Page 100
... Chapter 9, Triple Timer Module, discusses these registers. DSP56309 5-8 RXD Serial TXD SCLK Figure 5-5. Port E Signals TIO0 Timers TIO1 TIO2 Figure 5-6. Triple Timer Signals DSP56309 User’s Manual, Rev. 1 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2 Freescale Semiconductor ...
Page 101
... HAS HA0 — / host address line ( HA8 HA1 — / host address line ( HA9 HA2 Freescale Semiconductor ) or host multiplexed address/data bus ( H[0– host address line ( HAS HA0 ) or host address line ( HA8 HA1 ) or host address line ( HA9 HA2 DSP56309 User’s Manual, Rev. 1 ...
Page 102
... Freescale 68K family • Intel X86 family 6 read strobe ( HRD HRW ) or write strobe ( ) HDS HWR ) or host address line ( HCS ) or host transmit request ( HREQ ) or host receive request ( HACK DSP56309 User’s Manual, Rev HA10 ) HTRQ ) HRRQ ) all have HRD Freescale Semiconductor ...
Page 103
... HDR as an input signal if the HDDR bit is cleared output signal if the HDDR bit is set. For details, see Section 6.6.3, Host Data Direction Register (HDDR), on page 6-14 and Section 6.6.4, Host Data Register (HDR), on page 6-15. Freescale Semiconductor Non-multiplexed Bus Mode HAD[0–7] ...
Page 104
... RXM = Receive Register Middle RXL = Receive Register Low TXH = Transmit Register High TXM = Transmit Register Middle TXL = Transmit Register Low Figure 6-1. HI08 Block Diagram DSP56309 User’s Manual, Rev DSP HTX HRX Side 24 24 Host RXL TXH TXM TXL Side Freescale Semiconductor ...
Page 105
... The host can then use any of the available handshaking protocols to determine whether more data is ready to be read. The DSP56309 HI08 port offers the following handshaking protocols for data transfers with the host: Software polling Interrupts Core DMA access Host requests Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 Operation 6-5 ...
Page 106
... HSR, generating an interrupt request to the DSP56309 interrupt controller (see Figure 6-2). The DSP56309 acknowledges interrupts by jumping to the appropriate interrupt service routine. The following DSP core interrupts are possible from the HI08 peripheral: 6-6 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 107
... CVR[6–0] = HV[6–0] to select the interrupt address to be used. When the DSP core recognizes the host command interrupt, the address of the interrupt taken is 2xHV. For host command interrupts, the interrupt acknowledge from the DSP56309 program controller clears the pending interrupt condition. Freescale Semiconductor Enable 0 HF3 ...
Page 108
... Further, the host uses the ICR Receive Request Enable bit (ICR[0] = RREQ) and the ICR Transmit Request Enable bit (ICR[1] = TREQ) to enable receive and transmit requests, 6-8 Table 6-4. DMA Request Sources DSP56309 User’s Manual, Rev. 1 DCRx[15–11] = DRS[4–0] 10011 10100 Freescale Semiconductor ...
Page 109
... The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4. Freescale Semiconductor Status 0 HF2 TRDY ...
Page 110
... Little Endian bit (ICR[5] = HLEND). Big Endian mode is depicted in Figure 6-5. HTX/HRX Register: 23 DSP side Host side High Byte Host bus address: Host 32-bit internal register Figure 6-5. HI08 Read and Write Operations in Big Endian Mode 6- DSP56309 User’s Manual, Rev High Byte aa (read/write last Low Byte cc (read/write last Freescale Semiconductor ...
Page 111
... Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct memory mapping allows the DSP56309 core to communicate with the HI08 registers using standard instructions and Freescale Semiconductor / IRQA, MODA Table 6-7 ...
Page 112
... DSP-to-host communication protocol, implemented in both the DSP and the host processor software. The bit value is indeterminate after an individual reset. DSP56309 User’s Manual, Rev HF3 HF2 HCIE HTIE HRIE Description Freescale Semiconductor ...
Page 113
... Table 6-9. Host Status Register (HSR) Bit Definitions Bit Number Bit Name Reset Value 15–5 Freescale Semiconductor 0 Host Command Interrupt Enable Generates a host command interrupt request if the host command pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled ...
Page 114
... HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HRX register. The host processor can also clear HRDF using the initialize function DR8 DR7 DR6 DSP56309 User’s Manual, Rev. 1 Description DR5 DR4 DR3 DR2 DR1 DR0 Freescale Semiconductor 0 ...
Page 115
... Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5) Table 6-11. Host Base Address Register (HBAR) Bit Definitions Bit Number Bit Name Reset Value 15–8 7–0 BA[10–3] Freescale Semiconductor D10 HDR ...
Page 116
... HREN is set and HEN is set), then the HTRQ and HRRQ signals are active low outputs. If HRP is set and host requests are enabled, the HTRQ and HRRQ signals are active high outputs. DSP56309 User’s Manual, Rev. 1 Chip select Description Freescale Semiconductor 0 ...
Page 117
... HROD 7 6 HEN Freescale Semiconductor 0 Host Chip Select Polarity If the HCSP bit is cleared, the host chip select (HCS) signal is configured as an active low input and the HI08 is selected when the HCS signal is low. If the HCSP signal is set, HCS is configured as an active high input and the HI08 is selected when the HCS signal is high ...
Page 118
... Host GPIO Port Enable Enables/disables signals configured as GPIO. If this bit is cleared, signals configured as GPIO are disconnected: outputs are high impedance, inputs are electrically disconnected. Signals configured as HI08 are not affected by the value of HGEN. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
Page 119
... Host Receive (HRX) Register The HRX register is used in host-to-DSP data transfers. The DSP56309 views 24-bit read-only register. Its address is X:$FFFFC6 loaded with 24-bit data from the transmit data Freescale Semiconductor Figure 6-13. Single-Strobe Mode Write Data In Read Data Out Figure 6-14. Dual-Strobe Mode DSP56309 User’ ...
Page 120
... Reset Type HW SW Reset Reset $80 $ — — empty empty empty empty DSP56309 User’s Manual, Rev. 1 signal. The RESET IR ST Reset Reset — — — — — — — — — — — — empty empty empty empty Freescale Semiconductor ...
Page 121
... Stop mode, the core cannot be restarted via the HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you provide some other mechanism to exit stop mode. Freescale Semiconductor interrupt routines), and perform control or debugging DSP56309 User’s Manual, Rev. 1 ...
Page 122
... Register Name Interface Control Command Vector Interface Status Interrupt Vector Unused Receive/Transmit Data 1 0 Description After INIT Execution Transfer Direction INIT = 0 None INIT = 0; DSP to host RXDF = 0; HTDE = 1 INIT = 0; Host to DSP TXDE = 1; HRDF = 0 INIT = 0; Host to/from DSP RXDF = 0; HTDE = 1; TXDE = 1; HRDF = 0 Freescale Semiconductor ...
Page 123
... HF0 2 HDRQ 1 TREQ 0 RREQ Freescale Semiconductor 0 Reserved. Write to 0 for future compatibility. 0 Host Little Endian If the HLEND bit is cleared, the host can access the HI08 in Big-Endian byte order. If set, the host can access the HI08 in Little-Endian byte order. If the HLEND bit is cleared the RXH/TXH register is located at address $5, the RXM/TXM register at $6, and the RXL/TXL register at $7 ...
Page 124
... DSP set to $32 (vector location $064) by hardware, software, individual, and stop resets HF3 HF2 TRDY TXDE RXDF —Reserved bit; read as 0; write to 0 for future compatibility. DSP56309 User’s Manual, Rev HV1 HV0 Description 1 0 Freescale Semiconductor ...
Page 125
... HF2 2 TRDY 1 TXDE Freescale Semiconductor Host Request If HDRQ is set, the HREQ bit indicates the status of the external transmit and receive request output signals (HTRQ and HRRQ). If HDRQ is cleared, HREQ indicates the status of the external host request output signal (HREQ). The HREQ bit is set from either or both of two conditions— ...
Page 126
... RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF indicates whether the RX registers are full and data can be latched out (so that the host processor can use polling techniques IV6 IV5 IV4 IV3 IV2 DSP56309 User’s Manual, Rev. 1 Description 1 0 IV1 IV0 Freescale Semiconductor ...
Page 127
... RESET instruction. To reset the HEN bit individually, clear the HPCR[HEN] bit. To cause a stop reset, execute the STOP instruction. Table 6-18. Host-Side Registers After Reset Register Register Name Data ICR All bits CVR HC HV[0–6] Freescale Semiconductor signal. To cause a software reset, RESET Reset Type HW SW Individual Reset Reset Reset 0 0 — ...
Page 128
... HCS/A10 = GPIO 1 HCS/A10 = HCS DSP56309 User’s Manual, Rev. 1 STOP 1 if TREQ is set; 0 otherwise — — empty empty Reset Type HW/ Indivi- STOP SW dual 0 — — 0 — — 0 — — — — 0 — — 0 — — 0 — — 0 — — Freescale Semiconductor ...
Page 129
... Bus 12 HDDS Host Dual Data Strobe 13 HCSP Host Chip Select Polarity 14 HRP Host Request Polarity 15 HAP Host Acknowledge Polarity Freescale Semiconductor Bit Value Function HDRQ = 0 HDRQ = 1 0 HREQ/HTRQ = GPIO HREQ/HTRQ 1 HACK/HRRQ = GPIO HREQ/HTRQ = HREQ,HREQ/HTRQ HACK/HRRQ = HTRQ, HRRQ HDRQ = 0 HDRQ=1 0 HACK/HRRQ = GPIO ...
Page 130
... DSP56309 User’s Manual, Rev. 1 Reset Type HW/ Indivi- STOP SW dual — 0 — $80 empt y empt y $000 — 0 $000 — 0 Reset Type Indi HW/ Function vi-d SW ual 0 — 0 — 0 — 0 — 0 — 0 — 0 — Freescale Semiconductor — — — — STOP — — — — — — — ...
Page 131
... Host Command RXH/M/ 7–0 Host Receive Data Register L TXH/M/ 7–0 Host Transmit Data L Register IVR 7–0 IV[7–0] Interrupt Register Freescale Semiconductor Bit Name Value 0 Host Receive Register is empty 1 Host Receive Register is full 1 Host Transmit Register is 0 empty Host Transmit Register is full 1 ...
Page 132
... Host Interface (HI08) 6-32 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 133
... ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is still a synchronous device because all transfers are synchronized to these clocks. Pin notations for the generic ESSI refer to the analogous pin of ESSI0 ( Freescale Semiconductor GDB DDB RCLK ...
Page 134
... If sequential data words are 7-2 and SC0 SC1 DSP56309 User’s Manual, Rev signals are fully is an output when data is STD signal STD Freescale Semiconductor ...
Page 135
... SC0 the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as an output, functions as the serial Output Flag 0 (OF0 receive shift register clock SC0 Freescale Semiconductor ) when the ESSI function is not in use. P5 STD ) when the function is not in use ...
Page 136
... F1/T0D/U 1 TD1 F1/T0D/U 0 TD1 TD2 1 TD1 TD2 0 F0/U F1/T0D/U DSP56309 User’s Manual, Rev. 1 and ). STD SC1 function is not in use. is the transmitter data out SC1 ESSI Signals SC2 SCK STD SRD FST TXC TD0 FST TXC TD0 TD0 Freescale Semiconductor SC0 ...
Page 137
... When configured as an input, this signal receives an external frame sync signal for the transmitter in Asynchronous mode and for both the transmitter and receiver when in Synchronous mode. can be programmed as a GPIO signal ( SC2 not in use. Freescale Semiconductor RE SC0 SC1 1 F0/U ...
Page 138
... Write initial data to the transmitters that are in use during operation. This step is needed 4. even if DMA services the transmitters. 5. Enable the transmitters and receiver to be used. 7-6 signal, software reset instruction, ESSI individual reset, RESET DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 139
... TSR to clear the pending interrupt. ESSI transmit last slot interrupt: Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This Freescale Semiconductor DSP56309 User’s Manual, Rev. 1 Operation 7-7 ...
Page 140
... VBA (b23:8) p:I_SI0TD IPRP (S0L1:0) TX00 CRB (TE0) CRB0 (TIE) PCRC (PC[5–0]) SR (I1–0) DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 141
... DC[4–0] = $00000 in the CRA) with WL[2–0] = 100, the transmission does not work properly. To ensure correct operation, do not use On-Demand mode with the WL[2–0] = 100 32-bit word length mode. Freescale Semiconductor Operating Modes: Normal, Network, and On-Demand DSP56309 User’s Manual, Rev. 1 ...
Page 142
... Mixing frame sync lengths is useful in configuring systems in which data is received from one type of device (for example, codec) and transmitted to a different type of device. CRB[FSL0] controls whether RX and TX have the same frame sync length. If CRB[FSL0] is cleared, both RX and TX have the same frame sync length. 7-10 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 143
... MSB first. If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first. Freescale Semiconductor Operating Modes: Normal, Network, and On-Demand DSP56309 User’s Manual, Rev. 1 ...
Page 144
... Two Receive Slot Mask Registers (RSMA, RSMB), page 7-32 7-12 SC0 SC1 signal is not configured as the transmitter 0 drive-enabled SC1 is determined by the SCD1 bit. When SCD1 is set, SC1 is an input flag. SC1 DSP56309 User’s Manual, Rev configured as output. When flag is enabled when transmitter 2 Freescale Semiconductor ...
Page 145
... PSR —Reserved bit; read as 0; write to 0 for future compatibility. (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) Figure 7-2. ESSI Control Register A(CRA) Table 7-3. ESSI Control Register A (CRA) Bit Definitions Bit Number Bit Name Reset Value SSC1 0 Freescale Semiconductor WL0 ALC DC4 PM7 ...
Page 146
... If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use of 24- or 32-bit words leads to unpredictable results. Reserved. Write to 0 for future compatibility. DSP56309 User’s Manual, Rev. 1 WL0 Number of Bits/Word (valid data in the first 24 bits (valid data in the last 24 bits) 0 Reserved 1 Reserved Freescale Semiconductor ...
Page 147
... PM[7–0] 0 Freescale Semiconductor Description Frame Rate Divider Control Control the divide ratio for the programmable frame rate dividers that generate the frame clocks. In Network mode, this ratio is the number of words per frame minus one. In Normal mode, this ratio determines the word transfer rate. The divide ratio ranges from (DC = 00000 to 11111) for Normal mode and (DC = 00001 to 11111) for Network mode ...
Page 148
... TX Shift Register is the DSP56300 core internal CORE clock frequency. min = F /4096 OSC max = F /4 OSC CRB(SCD1) SYN = 0 SCn1 Sync: SYN = Flag1, or drive enb. Async . Flag1 Out, or drive enb. CRA(SSC1) CRB(TE2) CRB(OF1) (Sync Mode) CRB(SCD2) SCn2 Sync: TX/RX F.S. Async: TX F.S. Freescale Semiconductor ...
Page 149
... TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and set it again, then you disable the corresponding transmitter ( after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the Freescale Semiconductor ...
Page 150
... If the transmitter underrun error (TUE) bit is set (signaling that an exception has occurred) and the TEIE bit is set, the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
Page 151
... RE 16 TE0 15 TE1 Freescale Semiconductor 0 Receive Enable Enables/disables the receive portion of the ESSI. When RE is cleared, the receiver is disabled: data transfer into RX is inhibited. If data is being received while this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI receive data register. RE must be set in both Normal and On-Demand modes for the ESSI to receive data ...
Page 152
... When FSP is cleared, the frame sync signal polarity is positive; that is, the frame start is indicated by the frame sync signal going high. When FSP is set, the frame sync signal polarity is negative; that is, the frame start is indicated by the frame sync signal going low. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
Page 153
... SHFD 5 SCKD 4 SCD2 Freescale Semiconductor 0 Frame Sync Relative Timing Determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines for word length frame sync only. When FSR is cleared, the word length frame sync occurs together with the first bit of the data word of the first slot ...
Page 154
... SC0 signal is configured as ESSI flag 0. When SCD0 is set, the SC0 signal is an output. Data present in Bit OF0 is written to SC0 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
Page 155
... TX Serial Data Serial Clock RX Frame SYNC RX Serial Data TX Frame SYNC TX Serial Data Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0) Freescale Semiconductor Word Length: FSL1 = 0, FSL0 = 0 Data One Bit Length: FSL1 = 1, FSL0 = 0 Data Mixed Frame Length: FSL1 = 0, FSL0 = 1 Data Data ...
Page 156
... Frame Clock SYNC Clock Frame SYNC Receiver Figure 7-7. CRB SYN Bit Operation DSP56309 User’s Manual, Rev. 1 STD External Transmit Frame SC2 Internal Frame SYNC External Receive Frame SC1 SR ST External Frame SYNC SC2 Internal Frame SYNC SRD Freescale Semiconductor ...
Page 157
... Freescale Semiconductor Figure 7-8. CRB MOD Bit Operation DSP56309 User’s Manual, Rev. 1 ESSI Programming Model 7-25 ...
Page 158
... X:$FFFFB7, ESSI1 X:$FFFFA7) Figure 7-11. ESSI Status Register (SSISR) 7-26 Slot 0 Wait SLOT 0 SLOT RDF TDE ROE TUE DSP56309 User’s Manual, Rev. 1 Slot 0 SLOT 0 SLOT RFS TFS IF1 IF0 Freescale Semiconductor ...
Page 159
... ROE 4 TUE 3 RFS 2 TFS Freescale Semiconductor 0 Reserved. Write to 0 for future compatibility. 0 Receive Data Register Full Set when the contents of the receive shift register transfer to the receive data register. RDF is cleared when the DSP reads the receive data register. If RIE and RDF are set, a DSP receive data interrupt request is issued. ...
Page 160
... IF0 is enabled only when SC0 is an input flag and the Synchronous mode is selected; that is, when SC0 is programmed as ESSI in the port control register (PCR), the SYN bit is set, and the TE1 and SCD0 bits are cleared not enabled, the IF0 bit is cleared. DSP56309 User’s Manual, Rev. 1 Description Freescale Semiconductor ...
Page 161
... Transmit High Byte 7 23 Transmit High Byte STD 7 MSB 8-bit Data MSB 12-bit Data MSB MSB (b) Transmit Registers Figure 7-12. ESSI Data Path Programming Model (SHFD = 0) Freescale Semiconductor Receive Middle Byte Receive Low Byte Receive Middle Byte Receive Low Byte Bit ...
Page 162
... Least Significant 0 Zero Fill LSB NOTES: Data is received MSB first if SHFD = 0. 24-bit fractional format (ALC = 0). 32-bit mode is not shown. 0 ESSI Transmit Data Register (Write Only ESSI Transmit Shift Register 0 24 Bit ST 0 WL1, WL0 Least Significant Zero Fill LSB Freescale Semiconductor ...
Page 163
... TS11 TS10 TS9 TS8 —Reserved bit; read as 0; write for future compatibility. (ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4) Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA) Freescale Semiconductor TS7 TS6 TS5 TS4 DSP56309 User’s Manual, Rev. 1 ESSI Programming Model 15 ...
Page 164
... X:$FFFFB2, ESSI1 X:$FFFFA2) Figure 7-16. ESSI Receive Slot Mask Register A (RSMA) 7- TS23 TS22 TS21 TS20 RS7 RS6 RS5 RS4 DSP56309 User’s Manual, Rev TS31 TS30 TS29 TS28 TS19 TS18 TS17 TS16 RS15 RS14 RS13 RS12 RS3 RS2 RS1 RS0 Freescale Semiconductor ...
Page 165
... Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a PCR[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware signal or a software RESET instruction clears all PCR bits. RESET Freescale Semiconductor ...
Page 166
... PDRC[i] pr PDRD[i] bit reflects the value present on the input 7- PCx5 PCx4 PRx5 PRx4 DSP56309 User’s Manual, Rev PCx3 PCx2 PCx1 PRx3 PRx2 PRx1 Port Signal[i] Function ESSI0/ESSI1 Port C/Port D GPI Port C/Port D GPO Freescale Semiconductor 12 0 PCx0 12 0 PRx0 ...
Page 167
... PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD) Freescale Semiconductor ...
Page 168
... Enhanced Synchronous Serial Interface (ESSI) 7-36 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 169
... Intel 8051 serial interface mode 0 synchronizes data. Asynchronous modes are compatible with most UART-type serial devices. Standard RS-232 communication links are supported by these modes. Multidrop Asynchronous mode is Freescale Semiconductor DSP56309 User’s Manual, Rev 8-1 ...
Page 170
... Receivers with an address match can receive the message and optionally transmit an acknowledgment to the sender. The particular message format and protocol used are determined by the user’s software. 8-2 DSP56309 User’s Manual, Rev. 1 pin. To select SCLK Freescale Semiconductor ...
Page 171
... SCI functions. In this case, only one transmit interrupt can be generated because the Transmit Data Register is empty. The timer and timer interrupt operate regardless of how the SCI pins are configured, either as SCI or GPIO. Freescale Semiconductor , , and ) can be configured as either a GPIO signal or ...
Page 172
... SCI becomes active only PC2 PC1 PC0 DSP56309 User’s Manual, Rev. 1 SCLK ) PE0 ) when PE1 function is not in use. SCLK , since the clock TXD is independent of SCI data SCLK and data coming out the SCLK Freescale Semiconductor ) ...
Page 173
... Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO). ST Stop reset is caused by executing the STOP instruction. 1 The bit is set during this reset. 0 The bit is cleared during this reset. — The bit is not changed during this reset. Freescale Semiconductor Table 8-1. SCI Registers After Reset Bit Number HW Reset ...
Page 174
... If transmitter interrupt enable is set, an interrupt is issued and the interrupt handler should write data into the transmitter. The DMA channel services the SCI transmit request programmed to service the SCI transmitter. 5. Enable transmitters ( and receiver ( according to use. 8-6 . SCLK DSP56309 User’s Manual, Rev. 1 RESET pin. SCLK pin. SCLK Freescale Semiconductor ...
Page 175
... The next step is to receive the program size and then the starting address to load the program. These two numbers are three bytes each loaded least significant byte first. Each byte is echoed Freescale Semiconductor signal starts operation immediately after the SCLK ...
Page 176
... SCI Clock Control Register (SCCR) in Figure 8-4 Status — SCI Status Register (SSR) in Figure 8-3 Data transfer — SCI Receive Data Registers (SRX) in Figure 8-7 — SCI Transmit Data Registers (STX) in Figure 8-7 8-8 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
Page 177
... D7 (SSFTD = 1) Mode WDS2 WDS1 WDS0 TX Start D7 (SSFTD = 1) Data Type Address Byte 0 = Data Byte Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1 Freescale Semiconductor 8-bit Synchronous Data (Shift Register Mode One Byte From Shift Register 10-bit Asynchronous (1 Start, 8 Data, 1 Stop 11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop) ...
Page 178
... Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1. DSP56309 User’s Manual, Rev Stop D6 Data Bit Type D7 or Even Stop D6 Data Parity Bit Type D7 or Odd Stop D6 Data Parity Bit Type Stop Data D6 D7 Bit Type Freescale Semiconductor ...
Page 179
... SCI baud rate. The SCI internal clock is divided by 16 (to match the 1 × SCI baud rate) for timer interrupt generation. This timer does not require that any SCI signals be configured for SCI use to operate. Either a hardware RESET signal or a software RESET instruction clears TMIE. Freescale Semiconductor ...
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... Wait for TDRE to go high, indicating the last byte has been transferred to the transmit shift register. 3. Clear TE and set TE to queue an idle line preamble to follow immediately the transmission of the last character of the message (including the stop bit). 4. Write the first byte of the second message to STX. DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Thus, the received character is an address that has to be processed by all sleeping processors—that is, each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. Freescale Semiconductor Description DSP56309 User’s Manual, Rev. 1 SCI Programming Model ...
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... DSP56309 User’s Manual, Rev. 1 Word Formats 8-Bit Synchronous Data (shift register mode) Reserved 10-Bit Asynchronous (1 start, 8 data, 1 stop) Reserved 11-Bit Asynchronous (1 start, 8 data, 1 even parity, 1 stop) 11-Bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 11-Bit Multidrop Asynchronous (1 start, 8 data, 1 data type, 1 stop) Reserved Freescale Semiconductor ...
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... PE. In 10-bit Asynchronous mode, 11-bit multidrop mode, and 8-bit Synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver recognizes only the overrun error. Freescale Semiconductor ...
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... When set, TRNE indicates that the transmitter is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is no word in the transmit shift register being transmitted. This procedure is useful when initiating the transfer of a message (that is, a string of characters). 8-16 Description DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal. Thus, the SCLK output 11–0 CD[11–0] 0 Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected. Freescale Semiconductor SCP ...
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... Prescaler: 12-bit Counter Divide SCP CD[11–0] SCI Core Logic Uses Divide by 16 for Asynchronous Uses Divide by 2 for Synchronous DSP56309 User’s Manual, Rev. 1 Divide By 2 Internal Clock If Asynchronous Divide COD If Synchronous Divide By 2 SCKP = 0 + SCKP SCKP = 1 - SCLK Freescale Semiconductor ...
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... The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7. There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register. Freescale Semiconductor × clock) or the 16 0 ...
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... SCI Transmit Data Register Middle (Write Only) SCI Transmit Data Register Low (Write Only) STX TXD STXA SCI Transmit Data Address Register (Write Only) (b) Transmit Data Register signal are shifted into the SCI receive shift register. When a DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Asynchronous mode, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order. The data to be transmitted can be written to any one of the three STX Freescale Semiconductor TXD DSP56309 User’s Manual, Rev. 1 SCI Programming Model signal ...
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... GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the GPIO port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[ DSP56309 User’s Manual, Rev. 1 signal or a software RESET PE2/ PE1/ PE0/ SCLK TXD RXD Freescale Semiconductor ...
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... GPIO signal by the PCRE bits. For SCI, the GPIO signals are PE[2–0]. The corresponding data bits are PDRE[2–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 8-10. Port Data Registers (PDRE X:$FFFF9D) Freescale Semiconductor signal or a software RESET instruction clears all PRRE RESET ...
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... Serial Communication Interface (SCI) 8-24 DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and three timers. Each timer can use the prescaler clock as its clock source. Freescale Semiconductor is configured as an output, the timer functions as a TIO . TIO[0– ...
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... The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5. 9 TPCR Timer Prescaler Count Register Timer 0 Timer 1 Timer 2 DSP56309 User’s Manual, Rev Freescale Semiconductor ...
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... To initialize a timer, do the following: Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE] 1. bit. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt 2. enable bits as needed for the application. Freescale Semiconductor TCR TLR Load ...
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... Enable a specific peripheral interrupt. c. Unmask interrupts at the global level. d. Configure a peripheral interrupt-generating function. e. Enable peripheral and associated signals. 9-4 VBA (b23–8) p:TIM0C IPRP (TOL[1–0]) TCSR0 (TCIE) SR (I[1–0]) TCSR0 (TC[7–4]) TCSR0 (TE) DSP56309 User’s Manual, Rev. 1 Freescale Semiconductor ...
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... In Mode 0, the timer generates an internal interrupt when a counter value is reached, if the timer compare interrupt is enabled (see Figure 9-3 and Figure 9-4). When the counter equals the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is Freescale Semiconductor Mode Characteristics Mode ...
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... CLK) TLR Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TOF (Overflow Interrupt if TCIE = 1) 9-6 first event last event Figure 9-3. Timer Mode (TRM = 1) first event last event Figure 9-4. Timer Mode (TRM = 0) DSP56309 User’s Manual, Rev Freescale Semiconductor ...
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... Mode 1 (internal clock): TRM = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) TIO pin (INV = 1) Freescale Semiconductor Mode Characteristics Mode Name 1 Timer Pulse first event Figure 9-5. Pulse Mode (TRM = 1) DSP56309 User’ ...
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... This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). 9-8 first event pulse width = timer clock period Figure 9-6. Pulse Mode (TRM = 0) Mode Characteristics Mode Name 2 Toggle DSP56309 User’s Manual, Rev Function TIO Clock Timer Output Internal Freescale Semiconductor ...