XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 110

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three store
(or load) byte operations, ensuring that the data byte at host bus address $7 is written last since
this causes the transfer of the data to the DSP-side HRX. However, the host bus controller may be
sophisticated enough that the host can transfer all bytes in a single operation (instruction). For
example, in the PowerPC MPC860 processor, the General-Purpose Controller Module (GPCM)
in the memory controller can be programmed so that the host can execute a single read (load
word, LDW) or write (store word, STW) instruction to the HI08 port and cause four byte
transfers to occur on the host bus. The 32-bit datum transfer shown in Figure 6-4 has byte data xx
written to HI08 address $4, byte aa to address $5, byte bb to address $6 and byte cc to address $7
(this assumes the 24-bit datum is contained in the lower 24 bits of the host’s 32-bit data register
as shown).
A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing the Host
Little Endian bit (ICR[5] = HLEND). Big Endian mode is depicted in Figure 6-5.
6-10
Host side
Host side
DSP side
DSP side
internal register
internal register
Host 32-bit
Host 32-bit
Figure 6-4. HI08 Read and Write Operations in Little Endian Mode
Figure 6-5. HI08 Read and Write Operations in Big Endian Mode
HTX/HRX Bit Number: 23
HTX/HRX Register: 23
Host bus address:
Host bus address:
Low Byte
High Byte
xx
xx
DSP56309 User’s Manual, Rev. 1
$5
$5
cc
aa
cc
aa
aa
aa
bb
$6
bb
$6
bb
bb
bb
bb
aa
cc
$7
$7
aa
cc
cc
cc
0
0
(read/write last!)
(read/write last!)
Freescale Semiconductor
High Byte
Low Byte