AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 507

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

Figure 35-8. Data IN Transfer for Ping-pong Endpoint
6175K–ATARM–30-Aug-10
TXPKTRDY Flag
(UDP_MCSRx)
FIFO (DPR)
Bank 0
USB Bus
Packets
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Bank 1
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Set by Firmware,
Data Payload Written in FIFO Bank 0
Warning: There is software critical path due to the fact that once the second bank is filled, the
driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP
is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the
bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second
5. The microcontroller is notified that the first Bank has been released by the USB device
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB
7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay-
Data IN
PID
be cleared in the endpoint’s UDP_ CSRx register.
zero or more byte values in the endpoint’s UDP_ FDRx register.
FIFO by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register.
data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the
endpoint’s UDP_ FDRx register.
when TXCOMP in the endpoint’s UDP_ CSRx register is set. An interrupt is pending
while TXCOMP is being set.
device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end-
point’s UDP_ CSRx register.
load to be sent
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
Written by
Microcontroller
Read by USB Device
Data IN
Cleared by USB Device,
Data Payload Fully Transmitted
.
Set by USB
Device
AT91SAM7S Series Preliminary
ACK
PID
Interrupt Cleared by Firmware
Data IN
PID
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
Written by
Microcontroller
Set by Firmware,
Data Payload Written in FIFO Bank 1
Read by USB Device
Data IN
Set by USB Device
ACK
PID
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