AT91SAM7S128C-AU Atmel, AT91SAM7S128C-AU Datasheet - Page 245
![IC ARM7 MCU 32BIT 128K 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S128C-AU
Manufacturer Part Number
AT91SAM7S128C-AU
Description
IC ARM7 MCU 32BIT 128K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S256C-MU.pdf
(2 pages)
Specifications of AT91SAM7S128C-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S128-AU-001
AT91SAM7S128AU001
AT91SAM7S128AU001
AT91SAM7S128AU001
AT91SAM7S128AU001
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S128C-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 245 of 779
- Download datasheet (11Mb)
Figure 27-4. Output Line Timings
27.4.8
27.4.9
6175K–ATARM–30-Aug-10
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
Inputs
Input Glitch Filtering
PIO_ODSR
PIO_PDSR
MCK
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch filters are independently programmable on each I/O line. When the glitch fil-
ter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically
rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse
durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not
be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle
latency if the pin level change occurs before a rising edge. However, this latency does not
appear if the pin level change occurs before a falling edge. This is illustrated in
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.
It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The
glitch filters require that the PIO Controller clock is enabled.
APB Access
2 cycles
AT91SAM7S Series Preliminary
APB Access
2 cycles
Figure
27-5.
245
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