CY8C3866PVI-070 Cypress Semiconductor Corp, CY8C3866PVI-070 Datasheet - Page 107

• Manufacturer Part Number: CY8C3866PVI-070
• Description: IC MCU 8BIT 64KB FLASH 48SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866PVI-070

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 11-68. Synchronous Read Cycle Specifications
Document Number: 001-11729 Rev. *R
Note
T
Tcp/2
Tceld
Tcehd
Taddrv
Taddriv
Toeld
Toehd
Tds
Tadscld
Tadschd
47. Limited by GPIO output frequency, see
Parameter
EM_ ADSCn
EM_ Addr
EM_ CEn
EM_ OEn
EM_ Clock
EM_ Data
EMIF clock period
EM_Clock pulse high
EM_CEn low to EM_Clock high
EM_Clock high to EM_CEn high
EM_Addr valid to EM_Clock high
EM_Clock high to EM_Addr invalid
EM_OEn low to EM_Clock high
EM_Clock high to EM_OEn high
Data valid before EM_OEn high
EM_ADSCn low to EM_Clock high
EM_Clock high to EM_ADSCn high
Table 11-10
Description
[47]
Figure 11-69. Synchronous Read Cycle Timing
Tceld
Taddrv
Toeld
Tadscld
on page 74.
Tcp/2
Tadschd
Tds
Tcehd
Toehd
Data
Vdda ≥ 3.3 V
Address
Conditions
Taddriv
PSoC
T/2 – 5
T/2 – 5
T/2 – 5
T + 15
30.3
Min
T/2
T
5
5
5
5
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