ST16C2552IJ44-F Exar Corporation, ST16C2552IJ44-F Datasheet - Page 16

• Manufacturer Part Number: ST16C2552IJ44-F
• Description: IC UART FIFO 16B DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 485r

Specifications of ST16C2552IJ44-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 3.3 V ~ 5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 4 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1258-5

ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
.
SEE”RECEIVER” ON PAGE 12.
SEE”TRANSMITTER” ON PAGE 11.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
A
A2-A0
DDRESS
0 1 0
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
N
MCR
MSR
RHR
DLM
THR
FCR
LCR
SPR
AFR
R
LSR
DLL
IER
ISR
AME
EG
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Trigger
Enable
Global
FIFOs
T
B
Error
Input
Bit-7
Bit-7
Bit-1
CD#
Bit-7
Bit-7
Bit-7
ABLE
IT
0
0
0
-7
7: INTERNAL REGISTERS DESCRIPTION.
RX FIFO
Enabled
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Input
Bit-6
Bit-6
Bit-0
Bit-6
Bit-6
Bit-6
TSR
RI#
IT
0
0
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
Set Par-
Empty
DSR#
B
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
ity
IT
0
0
0
0
0
-5
16
Internal
Enable
Break
Parity
Loop-
CTS#
B
Even
Input
Bit-4
Bit-4
back
Bit-4
Bit-4
Bit-4
RX
IT
0
0
0
0
-4
Modem
Enable
Source
Enable
Enable
Control
Output
Fram-
Mode
Parity
OP2#
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Stat.
CD#
INT
Int.
RX
ing
IT
0
-3
RX Line
Source
(OP1#)
RXRDY#
Enable
Reset
Parity
B
Delta
FIFO
Rsvd
Error
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Select
Stat.
Stop
Bits
INT
RI#
Int.
RX
TX
IT
-2
Baudout#
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
RTS#
Over-
Word
B
FIFO
Error
Delta
Select
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
-1
rent Write
Control
Enable
Source
Enable
Length
Output
Ready
FIFOs
Concur-
DTR#
CTS#
B
Word
Delta
Data
Data
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
LCR[7] = 0
LCR[7] = 1
C
OMMENT
REV. 4.2.2