XR16L784IV-F Exar Corporation, XR16L784IV-F Datasheet - Page 11

• Manufacturer Part Number: XR16L784IV-F
• Description: IC UART 8B 3.3V QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L784IV-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1282

REV. 1.2.3
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
N
F
F
2.8.1
OTE
IGURE
IGURE
:
Table-B selected
Receive Data
Byte and Errors
8. R
9. R
16X or 8X Clock
64 bytes by 11-bit
Receive Holding Register (RHR) - Read-Only
ECEIVER
ECEIVER
wide
FIFO
16X or 8X Clock
as Trigger Table for
and Errors
Data Byte
O
O
Receive
PERATION IN NON
PERATION IN
Receive Data Shift
Register (RSR)
Figure 9
Data FIFO
FIFO
Receive
LSR bits
Receive
Tags in
Error
Data
4:2
-FIFO M
AND
Receive Data Shift
(Table
Register (RSR)
A
Holding Register
Receive Data
UTO
ODE
FIFO Trigger=16
Validation
14)
Data fills to 24
Data Bit
Data falls to 8
(RHR)
.
RTS F
Example: - RX FIFO trigger level selected at 16 bytes
11
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Validation
Data Bit
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
C
ONTROL
RHR Interrupt (ISR bit-2)
(See Note Below)
M
ODE
Receive Data Characters
Receive Data Characters
RXFIFO1
XR16L784
RXFIFO1