71M6511H-IGT/F Maxim Integrated Products, 71M6511H-IGT/F Datasheet - Page 16

• Manufacturer Part Number: 71M6511H-IGT/F
• Description: IC ENERGY METER RESIDENT 64-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6511H-IGT/F

• Processor Series: 6511x
• Core: 80515
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 7 KB
• Interface Type: I2C, SSI, UART
• Maximum Clock Frequency: 5 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: 71M6511H-DB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 22 bit Delta Sigma
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing
a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low ordered
bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very
slow external RAM or external peripherals.
Table 5 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of
the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table,
performs the MOVX instructions with a stretch value equal to 1.
CKCON.2
There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external
data RAM.
In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of
address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access
(256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX instruction (MOVX
A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large
data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and
two with paged access to the entire 64KB of external memory range.
Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is
used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data
pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB
of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.
The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently
selected DPTR for any activity.
The second data pointer may not be supported by certain compilers.
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CKCON register
0
0
0
0
1
1
1
1
CKCON.
1
0
0
1
1
0
0
1
1
CKCON.
0
0
1
0
1
0
1
0
1
Stretch Value
© 2005–2010 Teridian Semiconductor Corporation
Table 5: Stretch Memory Cycle Width
0
1
2
3
4
5
6
7
memaddr
Read signals width
Single-Phase Energy Meter IC
1
2
3
4
5
6
7
8
memrd
71M6511/71M6511H
DATA SHEET
1
2
3
4
5
6
7
8
memaddr
Write signal width
2
3
4
5
6
7
8
9
memwr
NOVEMBER 2010
1
1
2
3
4
5
6
7
V2.7