78M6612-DB/OMU-USB Maxim Integrated Products, 78M6612-DB/OMU-USB Datasheet - Page 43
78M6612-DB/OMU-USB
Manufacturer Part Number
78M6612-DB/OMU-USB
Description
KIT DEMO OUTLET MEASUREMENT OMU1
Manufacturer
Maxim Integrated Products
Datasheets
1.78M6612-IMF.pdf
(111 pages)
2.78M6612-EVM-1.pdf
(58 pages)
3.78M6612-DBOMU-USB.pdf
(30 pages)
4.78M6612-DBOMU-USB.pdf
(4 pages)
Specifications of 78M6612-DB/OMU-USB
Data Bus Width
8 bit
Interface Type
USB
Tool Type
Demonstration Board
Core Architecture
8051
Cpu Core
80515
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- 78M6612-IMF PDF datasheet
- 78M6612-EVM-1 PDF datasheet #2
- 78M6612-DBOMU-USB PDF datasheet #3
- 78M6612-DBOMU-USB PDF datasheet #4
- Current page: 43 of 111
- Download datasheet (2Mb)
DS_6612_001
1.5.7 Digital I/O
The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose
digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of
them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers
(DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or
The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O
RAM). Once declared as DIO, each pin can be configured independently as an input or output with the
DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as
DIO, to individually assign an internal resource such as an interrupt or a timer control.
direction registers and configurability associated with each group of DIO pins.
figuration for a DIO pin through its associated bit in its DIO_DIR register.
Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in
the Applications section and in
Rev. 1.2
power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control.
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups
16
22
23
N
x
–
–
–
–
–
0
0
Section 4.3 I/O Description
N
Y
1
5
7
6
0
1
1
1
7
1
2
1
3
1
1
DIO_DIR2
DIO2=P2
Y
2
3
3
2
2
1
8
–
–
–
–
–
Y
N
3
–
5
3
3
1
9
2
3
2
4
3
3
(SFR 0xA0)
–
–
(SFR 0xA1)
N
4
3
6
3
9
4
4
Y
2
0
4
4
4
7
4
4
N
Y
5
3
7
4
0
5
5
2
1
–
6
8
5
5
Y
6
3
8
4
1
6
6
2
2
–
–
–
–
under LCD_NUM[4:0].
Y
7
3
9
4
2
7
7
2
3
–
–
–
–
Y
8
4
0
4
3
0
0
9
4
1
4
4
1
1
Y
DIO_DIR1 (SFR 0x91)
DIO1=P1
1
0
4
2
4
5
2
2
Y
Table 39
Y
1
1
4
3
4
6
3
3
78M6612 Data Sheet
(SFR 0x90)
Table 38
shows the con-
1
2
–
–
–
–
–
1
3
–
–
–
–
–
lists the
1
4
2
0
2
1
6
6
–
43
1
5
2
1
2
2
7
7
–
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