AD6650/PCB Analog Devices Inc, AD6650/PCB Datasheet - Page 6

• Manufacturer Part Number: AD6650/PCB
• Description: BOARD EVAL FOR AD6650 W/SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6650/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6650

AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.
Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation
Parameter
WRITE TIMING
READ TIMING
1
2
Table 6. Microprocessor Port, Mode MNM (MODE = 1)
Parameter
WRITE TIMING
READ TIMING
1
2
Timing is guaranteed by design.
Specification pertains to control signals R/ W , WR , DS , RD , and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.
Timing is guaranteed by design.
DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor.
WR (R/W) to RDY (DTACK) Hold Time
Address/Data to WR (R/W) Setup Time
Address/Data to RDY (DTACK) Hold Time
WR (R/W) to RDY (DTACK) Delay
WR (R/W) to RDY (DTACK) High Delay
Address to RD (DS) Setup Time
Address to Data Hold Time
Data Three-state Delay
RDY (DTACK) to Data Delay
RD (DS) to RDY (DTACK) Delay
RD (DS) to RDY (DTACK) High Delay
DS (RD) to DTACK (RDY) Hold Time
R/W (WR) to DTACK (RDY) Hold Time
Address/Data to R/W (WR) Setup Time
Address/Data to R/W (WR) Hold Time
DS (RD) to DTACK (RDY) Delay
R/W (WR) to DTACK (RDY) Low Delay
DS (RD) to DTACK (RDY) Hold Time
Address to DS (RD) Setup Time
Address to Data Hold Time
Data Three-State Delay
DTACK (RDY) to Data Delay
DS (RD) to DTACK (RDY) Delay
DS (RD) to DTACK (RDY) Low Delay
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
HDS
HRW
SAM
HAM
DDTACK
ACC
HDS
SAM
HAM
ZD
DD
DDTACK
ACC
Symbol
t
t
t
t
t
t
t
t
t
t
t
HWR
SAM
HAM
DRDY
ACC
SAM
HAM
ZD
DD
DRDY
ACC
Rev. A | Page 6 of 44
2
2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
V
IV
IV
IV
IV
V
IV
V
IV
Test Level
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
Min
15.0
15.0
0.0
0.0
4 × t
15.0
0.0
0.0
4 × t
Min
0.0
0.0
0.0
9.0
4 × t
0.0
0.0
9.0
4 × t
CLK
CLK
CLK
CLK
Typ
16
13
16
Typ
12
Max
13 × t
0.0
13 × t
Max
15.0
13 × t
0.0
15.0
13 × t
CLK
CLK
CLK
CLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns