ATA5812-PLQ Atmel, ATA5812-PLQ Datasheet - Page 56
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ATA5812-PLQ
Manufacturer Part Number
ATA5812-PLQ
Description
IC TXRX UHF ASK/FSK 1CH 48-QFN
Manufacturer
Atmel
Datasheet
1.ATA5811-PLHC.pdf
(92 pages)
Specifications of ATA5812-PLQ
Frequency
315MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
ASK, FSK
Applications
Access Control, AMR, RKE
Sensitivity
-116dBm
Voltage - Supply
2.4 V ~ 3.6 V or 4.4 V ~ 6 V
Current - Receiving
10.5mA
Current - Transmitting
10.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 105°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Memory Size
-
Other names
ATA5812-PLQTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA5812-PLQW
Manufacturer:
ATMEL
Quantity:
962
11.1.7
Figure 11-8. Receiving Mode (TMODE = 1)
56
ATA5811/ATA5812
Receiving Mode
SDO_TMDO
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1'
Bit-check mode
If the Bit-check was successful for all bits specified by N
receiving mode. To activate a connected microcontroller, the bits VSOUT_EN and CLK_ON in
control register 3 are set to 1. An interrupt is issued at pin IRQ if the control bits T_MODE = 0
and P_MODE = 0.
If the transparent mode is active (T_MODE = 1) and the level on pin CS is low (no data transfer
via the serial interface), the RX data stream is available on pin SDO_TMDO
If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the
TX/RX data buffer (see
Manchester and Bi-phase coded signals. It is permanently possible to transfer the data from the
data buffer via the 4-wire serial interface to a microcontroller (see
Buffering of the data stream:
After a successful Bit-check, the transceiver switches from Bit-check mode to receiving mode. In
receiving mode the TX/RX data buffer control logic is active and examines the incoming data
stream. This is done, like in the Bit-check, by subsequent time frame checks where the distance
between two edges is continuously compared to a programmable time window as illustrated in
Figure 11-9 on page
coded signals are valid (T and 2T).
The limits for T are the same as used for the Bit-check. They can be programmed in control
register 5 and 6 (Lim_min, Lim_max).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Upper limit of 2T:
If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be round up.
Lim_min_2T
T
Lim_max_2T
T
Lim_min_2T
Lim_max_2T
=
=
=
=
Lim_min_2T
Lim_max_2T - 1
Lim_min
Lim_min
57, only two distances between two edges in Manchester and Bi-phase
+
'0'
+
Figure 11-9 on page
Lim_max
Lim_max
'1'
T
XDCLK
'0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
T
Receiving mode
XDCLK
–
+
Lim_max Lim_min
Lim_max Lim_min
–
–
57). The TX/RX data buffer is only usable for
2
2
Bit-check
Figure 10-1 on page
, the transceiver switches to
(Figure
4689F–RKE–08/06
11-8).
46).