ATMEGA128RZAV-8AU Atmel, ATMEGA128RZAV-8AU Datasheet - Page 173
ATMEGA128RZAV-8AU
Manufacturer Part Number
ATMEGA128RZAV-8AU
Description
MCU ATMEGA1281/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA128RZAV-8AU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
Operating Temperature Range
- 40 C to + 85 C
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega128
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- Download datasheet (10Mb)
18.2.1
2549M–AVR–09/10
Timing example
When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
Figure 18-3
ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 18-3. Output Compare Modulator, Timing Diagram
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC0A). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in
18-3
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.
(FPWM Mode)
(PORTB7 = 0)
(PORTB7 = 1)
(CTC Mode)
(Period)
at the second and third period of the PB7 output when PORTB7 equals zero. The period 2
OC1C
OC0A
clk
PB7
PB7
I/O
illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-
1
ATmega640/1280/1281/2560/2561
2
3
Figure
173
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